Koichi Sasada

Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor

In an SMT processor, the increase of the register contexts of a thread requires a large number of physical registers. Moreover, a physical register file in an SMT processor requires more ports for the execution units, which cause significant growth of the area, access time and power consumption of the register file. These problems are critical hurdles to implement a large scale SMT processor. Especially, growth of access time of a register file has a large impact on performance. In this paper, we propose a strategy to divide a physical register file into some banks and dynamic allocation of the banks to threads in order to reduce the access time of a register file. We have accomplished the reduction in access time of a register file up to 60% without growth of area by using the proposed strategy. On the contrary, IPC degradation can be limited up to 6% by this strategy