Mitaro Namiki

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Cube-2 is a prototype of building block scalable reconfigurable accelerator using an inductive coupling interconnect. It is consisting of a ultra low leakage embedded processor Geyser and coarse-grained reconfigurable accelerators CMA (Cool Mega Array). A Geyser chip and multiple CMA chips are stacked, and a powerful network is formed by using the inductive coupling interconnect. The performance can be enhanced by increasing the number of CMA chips. JPEG decoder is implemented with a cooperation of Geyser and CMAs, and low power execution by controlling the power supply voltage of CMAs is demonstrated.

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

CMA-Cube is the second prototype of building block scalable reconfigurable accelerator using inductive coupling interconnect. It uses the wireless inductive coupling interconnect as a packet switching network which connects accelerators. As an accelerator core, CMA (Cool Mega Array), which consists of a large coarse-grained PE array with combinatorial circuits and tiny micro-controller, is applied. Evaluation results of Cube-1 Quad Core which consists of a host embedded CPU and three CMA-Cubes achieved 3.15 times performance acceleration as that without accelerators when JPEG decoder is executed.

Delegation-Based MPI communications for a hybrid parallel computer with many-core architecture

Many-core architecture draws much attention in HPC community towards the Exascale era. Many ongoing research activities using GPU or the Many Integrated Core (MIC) architecture from Intel exist worldwide. Many-core CPUs have a great deal of impact to improve computing performance, however, they are not favorable for heavy communications and I/Os which are essential for MPI operations in general. We have been focusing on the MIC architecture as many-core CPUs to realize a hybrid parallel computer in conjunction with multi-core CPUs. We propose a delegation mechanism for scalable MPI communications issued on many-core CPUs so as to play delegated operations on multi-core ones. This architecture also minimizes memory utilization of not only many-core CPUs but also multi-core ones by deploying multi-layered MPI communicator information. Here we evaluated the delegation mechanism on an emulated hybrid computing environment. We show our innovative design and its performance evaluation on the emulated environment in this paper.

pmqFlow: Design of propagation time measuring QoS system with OpenFlow for process automation

This paper introduces a novel QoS architecture for process automation. The proposed architecture leverages the concept of Software Defined Network. The architecture maintains the real-time communications based on the measured propagation time. It maintains the configurations by detecting and predicting the change of propagation time in addition to queue usage. The authors utilize the OpenFlow with simple extension to measure the propagation time. The extension allows measuring propagation time with intelligent intermediate network equipment rather than changing process automation end-device. It is important requirement to keep the end-device untouched since the devices have small resources and applications are widely prevailed.

A design of hybrid operating system for a parallel computer with multi-core and many-core processors

This paper describes the design of an operating system to manage the hybrid computer system architecture with multi-core and many-core processors for Exa-scale computing. In this study, a host operating system (Host OS) on a multi-core processor performs some functions of a lightweight operating system (LWOS) on a many-core processor, in order to dedicate to executing the application program on a many-core processor. In particular, to ensure that LWOS execution does not disturb the application program executed on the many-core processor, the functions such as process management, memory management, and I/O management are delegated to the Host OS. To demonstrate this design, we made an prototype system of a computer equipped with a multi-core processor and a many-core processor using an Intel Xeon dual-core processor system. The Linux and original LWOS were loaded on to each processor and the overhead for executing the program for LWOS from Linux was evaluated. Using this prototype system, the LWOS process can be started with at least 110 μsec overhead for the many-core program.

Low-power distributed NoSQL database for IoT middleware

The Internet will become to the Internet of Things (IoT). It provides connectivity for everyone and everything that embeds some intelligence in Internet-connected objects to communicate, exchange information, take decisions, invoke actions and provide amazing services. This will bring a new ubiquitous computing and communication era and change peoples lives (drastically/entirely). Moreover, the most important component in IoT is database that used for collecting and storing a lot of data from ubiquitous sensing devices. Even though, cloud-based storage solutions are becoming increasingly popular in recent years, it is inconvenient for residential environments because the sensing devices should be connected to the internet for simultaneously sending data to cloud computing. However, this solution has a high cost implication and high power consumption. Therefore, the credit-card sized computer which is fully functional is a good alternative. It is small and inexpensive computer that provides a new opportunity for IoT hardware. As a result, it is possible to use Raspberry Pi as a database server. In this paper, we will explain how to construct a database server for IoT middleware that has data distribution and low-power consumption by using credit-card size computers which have satisfactory performances and affordable price.

A fine grained power management supported by just-in-time compiler

A low-power computing is now on high demand for both high performance computing and mobile computing. This research suggests the framework for controlling finely grained power saving hardware such as power gating, based on on-time analysis supported by JIT Compiler. By adapting the framework to control over fine-grained power gating control, the authors have succeeded to reduce the leakage power of processor by the maximum of 22%, and the average of 6%.

A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI

This paper describes a delegation based high throughput MPIcommunication mechanism under tough memory utilization constrains on a many-core oriented hybrid parallel computer. Towards the Exascale era, hybrid parallel computers consisting of many-core and multi-core architectures both on the same node are focused. Although many-core architectures such as GPU or Intel MIC has high potential in computing power by the large number of computing cores, per-core computing power is lower than that of multi-core CPUs. Furthermore, available memory resources for the many-core CPUs are quite smaller than those for multi-core CPUs. Thus we may have a sort of penalty in memory utilization in MPI communications when we utilize a normal MPI library. Here we deploy a delegatee process on each node to merge MPI communications and minimize memory utilization for an MPI communicator. Another advantage of the delegatee process scheme is minimization of memory utilization on many-core CPUs by delegating MPI requests to associated delegatee process on multi-core CPUs. In this paper, we show performance advantages and effective resource utilization by our proposed scheme compared with the original MPI implementation.

sQoS: The design and prototyping of secure QoS for process automation system

This paper presents the methods to prevent the QoS Spoofing attack, which disturbs the real-time network communications with malicious packets to delay or drop the control packets for Process Automation. The attack is new and unique threat introduced to the Process Automation, when the Process Automation users utilize wireless sensor network via plant wide backhaul network. sQoS is a HMAC based lightweight method to protect the real-time network communications from QoS Spoofing attack. This paper represents the design and prototyping of sQoS with the measurement result of its overhead time.

An efficient kernel-level blocking MPI implementation

The technique of user-level communication, where incoming messages wait in a busy loop, is used in most MPI implementations to achieve high communication performance. However, in some cases a kernel-level blocking receive is preferred. Some MPI implementations have an option to switch from user-level to kernel-level blocking with the sacrifice of communication performance. This paper identifies the problems when implementing kernel-level blocking receiving and proposes several techniques to avoid these problems. Evaluations show that the proposed kernel-level blocking techniques may achieve comparable performance with user-level communication.