Koichiro Tsujita

Sub-12nm optical lithography with 4x pitch division and SMO-lite

The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines and cuts” approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm.[1] In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant since mask data volumes of <500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMOLite” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole pitch division process to create a grid template combined with a relatively large “selection” pattern to create cuts at the desired grid locations. Experimental demonstration of the cut approach using SMO-Lite and a grid template will be presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the gate pitch at the 10nm node.

Characterization of 1D layout technology at advanced nodes and low k1

Highly regular gridded designs have been generally accepted1 as a key component for continued advances in lithographic resolution in an era of limited further progress in lithography hardware. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical Rayleigh limit ~ 0:25. High pattern densities (fine pitch) and good image quality and manufacturability are achieved by very regular designs Fig. 1, which avoid complex corner structures and pattern density variations typical for conventional 2D designs. In particular lines+cuts implementations of GDR are well-suited for pitch splitting and multiple patterning, where the critical cuts patterns can be easily separated into groups with larger pitch for separate patterning. Very advanced technology nodes thus become possible with conventional lithography technology, see2 for 11nm results.

Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization

A method to resolve 20nm node of SRAM contact layer whose minimum pitch is 90nm with enough process latitude is shown. To achieve the target by single exposure under condition of ArF and 1.35 of NA a way to optimize lithography parameters and layout parameters simultaneously is applied that is called co-optimization. At first the memory cell is optimized from several viewpoints of device and lithography, and then the entire memory cell block including the array circuit is optimized. It proves that combination of co-optimization and insertion of SRAF works very well considering the appropriate printed shape required by the device layout. The co-optimization is compared to such a conventional method as OPC. The performance is better than conventional OPC. Especially the MEFF is much better and the evaluation to find the mechanism is shown. It proves that complex patterns with many fragments make MEEF higher. The superior characteristics of co-optimization are analyzed by the result of Linear Programming that can find the strict solution. The pixel source shape has become almost same as one by co-optimization. The solution is achieved by binary mask with simple patterns and the simple source shape. It is crucial for COO.

Improvement of lithographic performance and reduction of mask cost by simple OPC

An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be competitive to a solution by complicated source shape and mask pattern. This technology is applied to cut pattern of 1 dimensional GDR layout of 20nm node and below. The simulation under ArF single exposure shows 16nm node of metal layer and 12nm node of gate layer can be resolved with rectangle mask patterns. For both layers bright field exposure is used and experimentally positive and negative tone developments are applied for metal layer (island patterns) and gate layer (cut patterns) respectively. The integrated process through SADP, etching, and so on is shown. It is found that the simple pattern has lower MEEF than the complicated ones. Applying simple mask pattern MEEF can be suppressed to be 3~4 even at 16nm node. The SEM images of the masks with simple and complicated shapes show that it is difficult to reproduce the complicated pattern accurately. We prepared mask data with various complexities of patterns and evaluated the writing time of an up-to-date EB writer. The time depends on the shot counts and a typical OPC pattern takes 4 times longer time than rectangle pattern. Since the cost of writing time is around 20% of the entire cost, the saved cost from OPC pattern to rectangle pattern becomes 15%. Regarding advanced node of mask with more complicated pattern it takes further longer time and there is an impact on other technologies of inspection or process. So the saved cost becomes huge.

Illumination optimization with actual information of exposure tool and resist process

A solution tool to optimize exposure tool functions has been developed. Shown are examples of pattern matching, maximizing ED-window or NILS considering several patterns simultaneously, and so on. From these results, the following conclusions have been derived. Pattern matching whose accuracy less than 1nm can be attained flexibly by tuning illumination. Ideal illumination for hole patterns through pitches are shown and the results are sensitive to setting of exposure latitude of ED-window. Evaluation conditions such as evaluated locations and their numbers have impact on the optimization results. An optimized illumination of a device pattern varies according to k1 factor. And it is important to apply OPC during illumination optimization in case of optimizing several patterns. A model of resist simulation created by an exposure condition should be available for various exposure conditions during optimization. For this purpose an image log slope and a pattern curvature have strong impact among various characteristics of optical image.

OPC-Lite for gridded designs at low k1

Highly regular gridded designs are generally seen as a key component for continued advances in lithographic resolution in a time of limited further progress in lithography hardware [1]. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical limit ∼ 0.25. A highly effective implementation of GDR is the lines+cuts approach discussed in [4, 5, 8] and else- where. Excellent results at very advanced nodes are achieved by this double-patterning process, where lines are created first, then cuts are patterned on top as required by circuit connectivity. The regular structure of gridded designs offers the opportunity to use an optimized approach to Optical Proximity Correction (OPC), one taking full advantage of the design style to achieve best possible ac- curacy and speed and at the same time small mask file size and good manufacturability. In this work we describe our GDR-tailored OPC tool called OPC- Lite [6]. The OPC-Lite approach is discussed and compared to conventional 2D OPC. Sub-20nm silicon data are shown, validating predictive quality of our simulation and OPC techniques.

Lithography and layout co-optimization beyond conventional OPC concept

Instead of conventional SMO that iterates illumination source optimization and OPC, new optimization method is introduced that optimizes illumination source and device layout simultaneously. In this method the layout is described by a function of layout parameters that defines the layout characteristics and the layout parameters are combined with source parameters, which forms a composite space of optimization. In this space the source and layout are optimized simultaneously. This method can search the steepest slope to the solution in the space during optimization, which is impossible for the conventional SMO. So it can reach the real solution with less probability of being trapped in local solution. This technology is applied to some cases of lithography targets such as CD and DOF, and good results are attained with very simple mask. It also works for diagonal patterns that OPC cannot handle easily. In addition more complicated lithography target such as robustness against MSD of scanner stage vibration is addressed and the optimization result is useful to resolve problems caused by fluctuation of manufacturing.

7nm logic optical lithography with OPC-Lite

The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout style with Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but with multiple patterning for critical layers. A “line/cut” approach is being used to achieve good pattern fidelity and process margin.[1] As shown in Fig. 1, even with “line” patterns, pitch division will eventually be necessary. For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while double patterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the need for triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final line dimensions can be achieved by applying pitch division by two or four.[5] In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOL layers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous experiments. Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with single patterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with double patterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimum pitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However these patterns can be separated by a combination of innovative SMO for less than optical resolution limit and a process trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin and local interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm) and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns of trims come from the simple 1D layout design. Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventional illuminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion with no complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.[5]

Pitch-based pattern splitting for 1D layout

The pattern splitting algorithm for 1D Gridded-Design-Rules layout (1D layout) for sub-10 nm node logic devices is shown. It is performed with integer linear programming (ILP) based on the conflict graph created from a grid map for each designated pitch. The relation between the number of times for patterning and the minimum pitch is shown systematically with a sample pattern of contact layer for each node. From the result, the number of times for patterning for 1D layout is fewer than that for conventional 2D layout. Moreover, an experimental result including SMO and total integrated process with hole repair technique is presented with the sample pattern of contact layer whose pattern density is relatively high among critical layers (fin, gate, local interconnect, contact, and metal).

11nm logic lithography with OPC-lite

CMOS logic at the 22nm node and below is being done with a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes have been demonstrated using a “lines and cuts” approach with good pattern fidelity and process margin, with extendibility to ~7nm.[1] In previous studies, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 12nm node.[2,3,4,5,6] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,7,8] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In our present work, we extend the scaling using SMO with “OPC Lite” beyond 12nm. The focus is on the contact pattern since a “hole” pattern is similar to a “cut” pattern so a similar technique should be useful. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous studies. The contact pattern is a relatively dense layer since it connects two underlying layers – active and gate – to one overlying layer – metal-1. Several design iterations were required to get suitable layouts while maintaining circuit functionality. Experimental demonstration of the contact pattern using OPC-Lite will be presented. Wafer results have been obtained at a metal-1 half-pitch of 18nm, corresponding to the 11nm CMOS node. Additional results for other layers – FINs, local interconnect, and metal-1 – will also be discussed.