Koji Sushihara

A mixed-signal 0.18-/spl mu/m CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD RAM and ROM systems. It integrates a 32-b RISC CPU, formatter, servo digital signal processor (DSP), 16-Mb DRAM, error correction code (ECC), ATA interface, and partial-response-maximum-likelihood (PRML) read channel with 7-b interpolated parallel analog-to-digital converter (ADC). Increasing the bus bandwidth by using embedded DRAM, a hardware ECC engine, and four parallel digital finite-impulse response (FIR) filters contributes to the high playback speed of 16/spl times/. PR(3,4,4,3) architecture has been used in the read channel system for optical disc systems. The obtained wide tangential tilt margin of /spl plusmn/0.6/spl deg/ is due to the use of this PRML read channel technique. The interpolated parallel scheme has attained a high number of effective bits of 6.3 for 72-Mz input frequency at 432-MSample/s operation without any calibration technique, with low power consumption of 180 mW in a small core size of 1.05 mm/sup 2/. This SoC has been fabricated in 0.18-/spl mu/m 1PS3AL CMOS embedded DRAM technology. It contains 24 million transistors in a 144-mm/sup 2/ die and consumes 1.2 W at 432-MSample/s operation. This low power consumption allows the use of a low-cost plastic package. As a result, we can compose highly reliable DVD RAM and ROM systems with this SoC and some tiny components.

A fully-integrated 0.13/spl mu/m CMOS mixed-signal SoC for DVD player applications

A mixed-signal SoC for DVD applications is designed in 0.13/spl mu/m 1P 6M CMOS. One DSP, two 32b RISC CPUs, three dedicated processing units, PRML read channel with an analog front end (AFE) and several other subsystems are integrated on the same die. The AFE contains a 5th-order G/sub m/-C filter and over 66dB C/N. The SoC contains 24M transistors in a 64mm/sup 2/ die and consumes 1.5W at 40MS/s which corresponds to 1.5/spl times/ DVD playback.

A 6 b 800 MSample/s CMOS A/D converter

In recent years, the demand for high-speed CMOS A/D converters has grown rapidly in digital read channel systems such as HDD. This 6 b CMOS ADC, attains 800 MSample/s conversion rate, the highest rate in CMOS implementation.

A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect

A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The ADC consumes 37.1 μW with 100 kHz sampling speed and achieves Schreiers figure of merit (FoMs) of 175.3 dB.

An 800-MHz 8-bit high speed SAR ADC in 16nm FinFET process

In this paper, we fabricated an 8-bit SAR ADC with a 16-nm FinFET process. A time-interleaved (TI-) ADC is remarked as an ADC with high speed sampling rate. Considering the area, the power consumption and the complexity of the mismatch calibration, it is possible that a unit SAR ADC of the TI-ADC with higher sampling rate improves these performances. We configure the SAR ADC with the high speed operation which is suitable for the advanced CMOS process and describe with the 16-nm FinFET process. Our SAR ADC achieves the 6.53 bits of ENOB with 800 MS/s. We compare other results with other process, and confirm that this SAR ADC can adapt to the advanced CMOS process.

High power efficient and scalable noise-shaping SAR ADC for IoT sensors

A high power efficient and scalable noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. 97.99 dB SNDR and 111.8 dB SFDR for 2 kHz bandwidth with only 37.1 μW power consumption is measured. By increasing sampling frequency, the performance of the ADC is changed to 93.95 dB SNDR and 108.0 SFDR for 20 kHz bandwidth with 493.1 μW power consumption.