Koki Abe

A Semi-Fragile Watermarking Scheme Using Weighted Vote with Sieve and Emphasis for Image Authentication

This paper describes a semi-fragile watermarking scheme for image authentication and tamper-proofing. Each watermark bit is duplicated and randomly embedded in the original image in the discrete wavelet domain by modifying the corresponding image coefficients through quantization. The modifications are made so that they have little effect on the image and that the watermarking is robust against tampering. The watermark image for authentication is reconstructed by taking a weighted vote on the extracted bits. The bits that lose the vote are treated as having been tampered with, and the locations of the lost bits as indicating tampered positions. Thus, authentication and tamper-proofing can be done by observing the images of watermarks that win and lose votes. Sieving, emphasis, and weighted vote were found to be effectively make the authentication and tamper detection more accurate. The proposed scheme is robust against JPEG compression or acceptable modifications, but sensitive to malicious attacks such as cutting and pasting.

An integrated laboratory for processor organization, compiler design, and computer networking

An integrated laboratory dealing with processor organization, compiler design, and computer networking has been developed. The goals of the laboratory are to make it possible for each student to work with modern and attractive materials and to learn about the interfaces between system modules, to provide students with opportunities to collaborate in the construction of a large system, and to give students a sense of accomplishment. The goals have been met based on the responses of students who have used it, verifying its effectiveness. This paper describes the design and development of the baseline components to be integrated, the laboratory organization and schedule, and the results and evaluation of the laboratory.

A Protocol Specification-Based Intrusion Detection System for VoIP and Its Evaluation

We propose an architecture of Intrusion Detection System (IDS) for VoIP using a protocol specification-based detection method to monitor the network traffics and alert administrator for further analysis of and response to suspicious activities. The protocol behaviors and their interactions are described by state machines. Traffic that behaves differently from the standard specifications are considered to be suspicious. The IDS has been implemented and simulated using OPNET Modeler, and verified to detect attacks. It was found that our system can detect typical attacks within a reasonable amount of delay time.

An integrated laboratory for computer architecture and networking

Processors, compilers, and networks -- important materials covered by computer science curricula -- are often treated independently in laboratories associated with corresponding lecture courses. An integrated laboratory called CNP for juniors majoring in computer science at the University of Electro-Communications has been developed and is now under way, where a networking protocol stack implemented by students is translated into object codes by a compiler implemented by students, which in turn are executed on a processor implemented also by students. The goals of the integrated laboratory are to deal with modern and attractive materials, to provide students with opportunities of collaborating in constructing a large system, as well as to have students share a feeling of accomplishments among them. Responses from students approved our intention and verified the effectiveness. In this paper, we describe the design and development of baseline components to be integrated, laboratory organizations and schedules, and results and evaluations of the laboratory.

A microcomputer implementation of PLA function and its use in a laboratory dealing with arithmetic algorithms

The function of a programmable logic array (PLA) was implemented using a microcomputer. The equipment is suitable for use in laboratories because it is electrically programmable, easy to be realized and maintained, and has sufficient capacity. It has been used for implementing fixed-point arithmetic algorithms, a subject of a laboratory course given to computer science majors of the University of Electro-Communications. The PLA program is created on a personal computer using a text editor and transmitted to the PLA through a serial communication line. Parallel interface circuits between the personal computer and the arithmetic unit to be implemented by the students were also prepared. The arrangements enable them to write and execute Pascal programs to test whether the implementation meets given specifications. >

A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits

We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 μm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.

Automatic measurement of frequency characteristics of operational amplifier circuits

Laboratory experiments were developed for measuring the frequency characteristics of operational amplifier circuits using a personal computer with a data acquisition unit. A periodic rectangular wave, which is easily generated by a DA (digital/analog) converter, is applied to the circuit: then the steady-state response is digitized by an AD converter. Filons method was used for the numerical Fourier integration of the sampled response. The errors associated with the measurement of the frequency characteristics of an integrator were found to be less than 0.2 dB and 1 degrees in gain and phase, respectively, within the frequency range satisfying the condition that the gain be >or=0 dB. >

Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption

A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.

A Microcomputer Laboratory--From Fundamentals to Interrupts and Queues

A microcomputer laboratory for juniors majoring in computer science was developed. It enables them to observe fundamental behavior of a computer by directly giving instructions to the CPU using a programmable diode array. The laboratory also includes experiments to synthesize a small microcomputer, with which advanced subjects such as interrupt processing and queue data structure usage are studied. As an application, a primitive interrupt‐driven graphics editor has been designed and implemented. Various circuit components were mounted on three panels, which facilitate for the students to construct required circuits. A personal computer has been used for software development.