Kong Boon Yeap

Determining interfacial properties of submicron low-k films on Si substrate by using wedge indentation technique

This article presents studies on using a wedge indentation technique to determine interfacial adhesion properties of low-k dielectric films, namely, methyl-silsesquioxane (MSQ) and black diamond (BD™)films, both on a Si substrate. Interfacial crack initiation and propagation processes in the MSQ/Si system are studied by using focused-ion-beam sectioning of the indentation impressions created by wedge tips with 90° and 120° of inclusion angles, respectively. Furthermore, the indentation induced stress is found to be proportional to the ratio of the indentation volume and the interface delamination crack volume for both plane strain and nonplane strain cases. With this analysis, the interface toughness of the MSQ/Si and BD/Si system, in terms of the strain energy release rate, is determined. The interface toughness for the MSQ/Si system is found to be a value of 1.89±0.28J∕m2 for the 90° wedge tip indentation and 1.92±0.08J∕m2 for the 120° wedge tip indentation. In addition, using the 120° wedge tip, the in...

In situ study on low-k interconnect time-dependent-dielectric-breakdown mechanisms

An in situ transmission-electron-microscopy methodology is developed to observe time-dependent dielectric breakdown (TDDB) in an advanced Cu/ultra-low-k interconnect stack. A test structure, namely a “tip-to-tip” structure, was designed to localize the TDDB degradation in small dielectrics regions. A constant voltage is applied at 25u2009°C to the “tip-to-tip” structure, while structural changes are observed at nanoscale. Cu nanoparticle formation, agglomeration, and migration processes are observed after dielectric breakdown. The Cu nanoparticles are positively charged, since they move in opposite direction to the electron flow. Measurements of ionic current, using the Triangular-Voltage-Stress method, suggest that Cu migration is not possible before dielectric breakdown, unless the Cu/ultra-low-k interconnect stacks are heated to 200u2009°C and above.

Finite element simulation and experimental determination of interfacial adhesion properties by wedge indentation

This paper presents our recent study on determination of interfacial adhesion properties of soft-film-on-hard-substrate (SFHS) systems using finite element simulation (FEM) and wedge indentation experiments. The objectives of this study are: (i) to simulate the interfacial delamination processes during wedge indentation experiments; (ii) to study the effects of interfacial delamination on the characteristics of the indentation load–displacement (P–h) curves, (iii) to determine the interfacial adhesion properties; and (iv) to compare the simulation and experimental results. During the FEM simulation, a traction-separation law is used to describe the interfacial adhesion properties due to the large-scale yielding during indentations. The effects of main parameters in the traction-separation law, i.e. interfacial strength and interfacial energy, to the initiation of interfacial delamination are studied by parametric studies. An interface energy-strength contour, which can be used to determine the interfacial adhesion properties of the thin-film/substrate systems based on a wedge indentation experiment, is developed from the outcomes of the FEM simulation of the indentations using wedge tips with the inclusion angles of 90° and 120°. Using the respective interface energy-strength contours, the interfacial energy and strength of a BlackDiamond® (BD)/Si system and a methylsilsesquioxane (MSQ)/Si system are determined. The simulated results are then compared with the previous experimentally derived interfacial fracture toughness values and some further discussions are given.

Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability

The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for <; 3μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage/Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed to analyze FEOL reliability for degradation phenomena such as Voltage Break Down (VBD), Hot Carrier Injection (HCI), and Bias Temperature stability (BTI). Test structures were designed to investigate TSV impact on the lower metal and via levels of the BEOL stack. BEOL reliability analysis for degradation phenomena such as Time Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Migration (SM) were performed to investigate any potential impact to due to TSV mechanical stress or Cu pumping effects. BEOL Our investigations showed no significant impact to FEOL or BEOL test structures due to the TSV via middle approach.

Advanced concepts for TDDB reliability in conjunction with 3D stress

Time-Dependent Dielectric Breakdown (TDDB) in the Backend-of-Line (BEoL) stack has become one of the most important failure mechanisms for state-of-the art integrated circuits and threatens the long-term reliability of advanced semiconductor products. The continuous reduction in the BEoL feature sizes, resulting in continuously smaller spacing between interconnects, along with a slower pace in the reduction of the operational voltages, has led to significantly increased electrical fields. In addition, the introduction of low-k and ultra-low-k (ULK) materials has complicated the situation even more, since lifetimes for those materials are typically several decades shorter than for traditionally used SiO2. While the reliability community has mostly adopted the square-root-E model for backend dielectric failure and has abandoned the more conservative linear-E-model, major questions about the true physical mechanism of dielectric failure, such as the role of Cu, still exist. Within the context of More than M...

Optimizing Cu barrier thickness for interconnects performance, reliability and yield

Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.