Patrick Justison

Stress migration model for Cu interconnect reliability analysis

Stress migration (SM) reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative SM analysis and lifetime estimates for products were not available due to lack of a suitable SM model. In this paper, we establish a comprehensive SM model for quantitative stress-induced-voiding (SIV) risk analysis for 32 nm technology and beyond. It was found that the SIV risk is dependent on both stress temperatures and geometric structural line widths as driving forces. Based on the new SM model, the SM lifetime can be estimated from measurable SM data and accelerated SM test methods can be designed to meet the qualification criteria.

A Realistic Method for Time-Dependent Dielectric Breakdown Reliability Analysis for Advanced Technology Node

This paper proposes a methodology to determine a realistic time-dependent dielectric breakdown failure rate. The in-die constant voltage stress was performed to determine the chip level Weibull shape (βdie) and voltage acceleration factor, while a voltage ramp (Vramp) is performed in production line (inline Vramp) to determine the via-to-line and line-to-line spacing distributions. We found that for the chip population with spacing (s) smaller than 4 nm, the in-die voltage accelerations based on power-law and sqrt-V models do not lead to a significant difference in the lifetime prediction. For the chips with large spacing, the stress voltage (~20 V) is significantly higher than the operating voltage (1 V). The extrapolation using the power law results in an infinitely long lifetime, which could lead to an overoptimistic reliability prediction. In this paper, a new method is introduced for a more realistic failure rate calculation, which is the superposition of the failure rates of chips with small spacing (s <; 4 nm) and the failure rates of chips with large spacing, by using different voltage acceleration models.

Stress-induced-voiding risk factor and stress migration model for Cu interconnect reliability

SM reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative stress-induced-voiding (SIV) risk analysis and lifetime estimates for products were not available due to lack of quantitative data and a suitable SM model. In this paper, we provide quantitative analysis of SIV risk based on geometry factors and further establish a comprehensive SM model for SM lifetime estimation for 32nm technology and beyond. An SIV risk factor is defined to quantify the relative risks of Cu BEOL interconnect structures. Based on the new SM model, an effective geometry factor was found for an accelerated SM test method to perform SM lifetime estimation from measurable SM data.

Scaling effects on microstructure and electromigration reliability for Cu and Cu(Mn) interconnects

EM reliability of Cu and Cu(Mn) interconnects was investigated, focusing on the scaling effect on grain structure and mass transport. The microstructure of Cu and Cu(Mn) interconnects was characterized up to the 22 nm node using a high-resolution TEM diffraction technique. Compared to Cu interconnects of the 45 nm node, the 28 nm Cu(Mn) structures were found to have a strong {111} texture along the line length direction and a low fraction of coherent twin boundaries (~2%). Inclusion of Mn was found to be important for microstructure evolution. The effect of Mn alloying on EM reliability was examined by comparing the lifetime statistics to Cu interconnects with standard SiCN cap and CoWP metal cap. The interfacial and GB diffusivities together with activation energies were extracted from resistance traces in EM tests. Mn was found to effectively reduce EM-induced mass transport, particularly for interfacial diffusion. These results were combined to project the Mn alloying effect for future technology.

Electromigration reliability of Mn-doped Cu interconnects for the 28 nm technology

Electromigration (EM) reliability of Cu interconnects for the 28 nm node with Mn doping was studied by investigating the effects of line width and length on void formation kinetics, EM lifetime and statistics. Failure modes and mass transport mechanism responsible for EM degradation of CuMn interconnects were examined. Although immortality was not observed, EM lifetime of short lines was significantly improved together with a reduction in lifetime deviation. This is attributed to the effectiveness of Mn in repairing process defects, particularly for via-related void formation in V1M2 electron flow direction.

Impact of TSV process on 14nm FEOL and BEOL reliability

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

A Predictive Model for IC Self-Heating Based on Effective Medium and Image Charge Theories and Its Implications for Interconnect and Transistor Reliability

Spatially resolved precise prediction of local temperature <inline-formula> <tex-math notation=LaTeX>

Impact of electrode surface modulation on time-dependent dielectric breakdown

{T}(textit {x,y,z})

An investigation of dielectric thickness scaling on BEOL TDDB

</tex-math></inline-formula> is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, especially for fast turn-around reliability modeling. Here, an analytical model that can quickly/accurately determine <inline-formula> <tex-math notation=LaTeX>

Vertical natural capacitor time dependent dielectric breakdown (TDDB) improvement in 28nm

textit {T(x,y,z)}