Kong-pong Pun

A Low-power BitStream Controller for H.264/AVC Baseline Decoding

In this paper, the authors present the design and VLSI implementation of a low-power bitstream controller for H.264/AVC baseline profile decoding. It is comprised of bitstream parsing and three dedicated decoders for intra-prediction mode, inter-motion vector and boundary strength. Various low-power design techniques, such as statistic-based data driven decoding, hierarchical FSM decomposition, nonuniform LUT partition favoring smaller tables, module-wise clock gating are employed. Due to a clever architecture design, the proposed work is capable of decoding realtime QCIF of 30 fps at a required operating frequency as low as 1MHz or even slower. A prototype chip, fabricated in a 0.18mum CMOS process, has an area of 3.6mm2 with 47k gate counts and dissipates 113muW of power on a 1.8V supply

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder

In this paper, we propose a power-efficient bitstream parsing for H.264/AVC baseline profile decoding. It parses the input bitstream syntaxes and controls the following decoding steps. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, clock gating etc., have been adopted in our design. The VLSI implementation results show that under UMC130nm technology with 1.08V supply voltage, the core power consumption is only 1.98mW@20MHz for real-time decoding. Total hardware costs are 49k gates and 1.2 times 1.2mm2 chip area. The power-efficient and real-time features make our design ideal for low-power video transmission applications such as mobile phone and PDA where video quality is often traded off for energy

Design for self-checking and self-timed datapath

This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

Current mode 900 MHz CMOS mixer

This paper presents the design and measurement results of a 1.2 V 900 MHz CMOS mixer. We use current mode multiplication instead of voltage mode multiplication to reduce the operating voltage to 1.2 V. Moreover, the new mixer has a good linearity; the measured input-referred 1-dB compression point and the Third-order Input Intercept Point (IIP3) are 3 dBm and 10 dBm respectively. The new mixer-circuit is specially designed for low voltage communication circuits using RF CMOS. The measured power dissipation of the mixer is 3 mW from a single 1.2 V voltage supply. A test circuit has been fabricated with 0.6 µm CMOS technology. The new multiplier cell occupies an area of 400 µm × 400 µm.

A high-efficiency strongly self-checking asynchronous datapath

This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

A high image rejection continuous-time IF sigma-delta ADC with time-sharing of input resistors

In this paper, a novel resistor time-sharing technique is proposed to achieve higher image rejection in an intermediate frequency (IF) continuous-time (CT) sigma-delta (/spl Sigma//spl Delta/) analog-digital converter (ADC) with lowpass noise-shaping and integrated IF switching mixers. A second order modulator is used to test the image rejection performance of the overall circuit. Simulation in Matlab gives perfect image rejection performance.

Design of a CMOS active RC baseband channel filter for a direct conversion WCDMA receiver

The direct conversion receiver architecture achieves a high integration level because off-chip passive image and channel selection filters are not needed like in superheterodyne. The channel selection can be performed with integrated analog or digital filters. This paper reports the design of a baseband channel selection for a 3G WCDMA direct conversion receive, which consists of a channel selection filter with automatic tuning scheme and a programmable gain amplifier (PGA) merged into filter chain. The design provides solutions to some known problems of direct conversion receivers such as DC offset (DC servo feedback technique). Active RC integrator is used in the filter chain (5th-order Chebyshev with 0.01dB ripple and -3 dB frequency close to 2 MHz) and a fully differential telescopic two-stage operational amplifier is chosen.

A totally self-checking dynamic asynchronous datapath

This paper investigates the inherent totally self-checking (TSC) property of one type of dynamic asynchronous datapath based on Differential Cascode Voltage Logic (DCVSL). As a result, a totally self-checking dynamic asynchronous datapath architecture is proposed. It is simpler than other similar approaches and represents a new approach to fault tolerant design.

Pipelines in dynamic dual-rail circuits

This work investigates the inherent relations among latch-free dynamic pipelines (LFDP). Approaches to self-checking (SC) LFDP design are also presented.

Mismatch improvement for high image rejection in two path switched-capacitor sigma-delta modulators

In IF-sampling A/D converters employing lowpass sigma-delta modulators, the mismatches between the in-phase (I) and quadrature-phase (Q) channels, including the mismatch between the I and Q sampling capacitors, will limit their image rejection performance. In this paper, a technique of sharing front-end sampling capacitor pairs between I and Q channels is proposed to eliminate their mismatch and thus to improve the image rejection performance of the IF-sampling ADC. Behavioral simulation results are presented to demonstrate the technique.