Chiu-Sing Choy

An efficient MFCC extraction method in speech recognition

This paper introduces a new algorithm of extracting MFCC for speech recognition. The new algorithm reduces the computation power by 53% compared to the conventional algorithm. Simulation results indicate the new algorithm has a recognition accuracy of 92.93%. There is only a 1.5% reduction in recognition accuracy compared to the conventional MFCC extraction algorithm, which has an accuracy of 94.43%. However, the number of logic gates required to implement the new algorithm is about half of the MFCC algorithm, which makes the new algorithm very efficient for hardware implementation

Reversed nested Miller compensation with voltage buffer and nulling resistor

This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-/spl mu/m CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation.

A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC

This paper describes the design and VLSI implementation of a highly efficient, single-port SRAM-based deblocking filter. It can achieve 204 cycles/macroblock throughput for H.264/AVC real-time decoding. Several deblocking filter designs in the literature have been compared and the possibility of realizing them in a pipeline is studied. Eventually we came up with a completely new design which has a five-stage pipeline with gated clock to increase system throughput while reducing power. Data hazards and structure hazards, which are the two most critical issues for a pipelined filter, are analyzed and resolved. Efficient memory organization for both on-chip SRAM and transposition buffers is employed. By using innovative hybrid edge filtering sequence and out-of-order memory update scenario, we obtain zero stall cycle in normal pipeline flow, making the best out of a pipelined architecture. Compared with existing designs, our design achieves at least 18% clock cycle reduction, as well as 20% lower power consumption owing to its efficient pipeline and memory architecture. The total gate count is comparable to other designs in literature without using any expensive two-port or dual-port on-chip SRAMs.

A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding

Prediction, including intra prediction and inter prediction, is the most critical issue in H.264/AVC decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and account for up to 80% of the total decoding cycles. In this paper, we present the design and VLSI implementation of a novel power-efficient and highly self-adaptive prediction engine that utilizes a 4 times 4 block level pipeline. Based on the different prediction requirements, the prediction pipeline stages, as well as the correlated memory accesses and datapaths, are fully adjustable, which helps to reduce unnecessary decoding operations and energy dissipation while retaining the fixed real-time throughput. Compared with conventional designs, this paper has the advantage of higher efficiency and lower power consumption due to the elimination of all redundant operations and the wide employment of the pipeline and parallel processing. Under different prediction modes, our design is able to decode each macroblock within 500 cycles. A prototype H.264/AVC baseline decoder chip that utilizes the proposed prediction engine is fabricated with UMC 0.18-mu CMOS 1P6 M technology. The prediction engine contains 79 K gates and 2.8 kb single-port on-chip SRAM, and occupies half of the whole chip area. When running at 1.5 MHz for QCIF 30 f/s real-time decoding, the prediction engine dissipates 268 muW at a 1.8-V power supply.

A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions

Semicustom IC design methodologies often assume a wide range of operating conditions. This requirement makes designing output drivers very difficult, as output ringing due to overdriving cannot be avoided. This problem becomes more tricky when power noise due to simultaneous switching of many output drivers at very high speed is also considered. A new output driver is proposed that adopts an innovative feedback mechanism to achieve an adaptive characteristic so that its performance will not vary under different loading conditions. The driver is also low in power noise as it works with a principle similar to a controlled slew rate output driver. Measurement from a test chip substantiates all those claims.

A feedback control circuit design technique to suppress power noise in high speed output driver

In todays sub-micron CMOS integrated circuit technology, high speed output switching signals interacting with external inductance and capacitance produce noise which contaminates output signals and power buses. A Feedback Control Slew Rate Output Driver (FCSROD) which reduces the noise spike down to approximately 64% of a conventional output buffer without incurring the penalty of the propagation delay and even the rise/fall time is described. This effective power noise suppression is achieved by using distributed and weighted switching driver segments in conjunction with feedback control to control the output drivers slew rate. Dynamic short circuit current which is generated while both pFET and nFET are conducting is also minimized to reduce di/dt noise. FCSROD was compared with a conventional and the controlled slew rate output buffer, showing 64% noise reduction comparing to the conventional driver, and 22% improvement in both propagation delay and rise/fall time comparing with the controlled slew rate output driver.

An ECG measurement IC using driven-right-leg circuit

In this paper, an electrocardiographic (ECG) signal processing IC, which is used for portable biomedical application, was designed using continuous-time technique. The circuit consists of an instrumentation amplifier (INA) with driven-right-leg circuit (DRL), a 5th order Gm -C low pass filter (Gm-C LPF) operating in sub-threshold mode, and amplifiers. DRL circuit is used to detect small amplitude signal in the presence of large common-mode voltage from the human body. The CMRR of the INA is 78 dB and the Gm-C LPF has a cutoff frequency of 18 Hz. As a result of using the DRL, a small signal can be detected in the presence of large common-mode differential. The circuit consumes 1.23 mW when operating from with a supply voltage of plusmn1.5-V and occupies a core area of 0.94 mm2. The circuit was designed in a 0.35mum CMOS process and simulation results have successfully demonstrated the functionalities

An HMM-based speech recognition IC

This paper presents the design, simulation and measurement results of a Hidden Markov Model (HMM) based isolated word recognizer IC with double mixtures. Table look-up technique is employed in this design. The chip operates at 20 MHz at 3.3 V. The recognition time is 0.5 s for a 50-word speech library. The speech IC has been verified with 467 test speech data and the recognition accuracy is 93.8%. A reference software recognizer using the same algorithm and speech library has a recognition accuracy of 94.2%. The new speech IC that uses a table look up to reduce the complexity of the circuit has approximately the same recognition accuracy as an ideal software recognizer.

A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers

A band-selective low-noise amplifier (BS-LNA) for multiband orthogonal frequency-division multiplexing ultra-wide-band (UWB) receivers is presented. A switched capacitive network that controls the resonant frequency of the LC load for the band selection is used. It greatly enhances the gain and noise performance of the LNA in each frequency band without increasing power consumption. Moreover, a fully differential configuration is employed to suppress the common-mode switching noise that is generated during the band transition interval. Fabricated in a 0.18-mum CMOS process, the BS-LNA achieves a peak power gain of 16 dB, a minimum noise figure of 2.74 dB, and an third-order input intercept point of -8.8 dBm at a current consumption of 7.95 mA from a 1.5-V supply. Little performance degradation is observed when the current consumption is reduced by half. The experimental results also show a worst-case band-switching time of less than 3.4 ns, with a peak switching noise voltage of less than 70 muV at the output.

Incremental layout placement modification algorithms

Many circuit modifications require only a slight adjustment to the IC layouts. General purpose placement algorithms cannot take advantage of these situations because they are designed to generate a complete placement from scratch. In this paper, we present two new algorithms to effect incremental changes on a gate array layout automatically. The algorithms will selectively relocate a number of logic elements to vacate an empty slot. The empty slot is then ready for an added logic element. Results obtained prove that the two algorithms are superior over simple-minded layout modification methods. The computation time is of O(n/sup 3/2/) where n is the number of elements in the neighborhood of change in a layout. For conventional placement algorithms, n will include all the elements in the layout. Therefore, the incremental algorithms will be several orders of magnitude faster.