Konosuke Watanabe
Keio University
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Publication
Featured researches published by Konosuke Watanabe.
cluster computing and the grid | 2003
Konosuke Watanabe; Tomohiro Otsuka; Jun Ichiro Tsuchiya; Hideharu Amano; Hiroshi Harada; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh
RHiNET-2/NI is a network interface for a parallel and distributed computing system with network connected PCs. The core of the network interface is an ASIC network controller chip Martini, which provides low-latency and large-bandwidth communication. Evaluation results show that it achieves almost full bandwidth of the 66MHz/64bit PCI bus, which is much larger than that of Myrinet-2000. The performance of a small prototype parallel system achieves almost linear speed up.
IEEE Transactions on Parallel and Distributed Systems | 2007
Konosuke Watanabe; Tomohiro Otsuka; Junichiro Tsuchiya; Hiroaki Nishi; Junji Yamamoto; Noboru Tanabe; Tomohiro Kudoh; Hideharu Amano
In this paper, “Martini,” a network interface controller chip for our original network called RHiNET is described. Martini is designed to provide high-bandwidth and low-latency communication with small overhead. To obtain high performance communication, protected user-level zero-copy RDMA communication functions are completely implemented by a hardwired logic. Also, to reduce the communication latency efficiently, we have proposed PIO-based communication mechanisms called “On-the-fly (OTF)” and have implemented them on Martini. The evaluation results show that Martini connected to a 64bit/66MHz PCI-bus achieves 470MByte/s maximum bidirectional bandwidth and 1.74 μsec minimum latency on host-to-host memory copying.
parallel and distributed computing: applications and technologies | 2005
Akira Kitamura; Yasuo Miyabe; Tetsu Izawa; Tomotaka Miyashiro; Konosuke Watanabe; Tomohiro Otsuka; Hideharu Amano; Yoshihiro Hamada; Noboru Tanabe; Hironori Nakajo
By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot by using the indirect accessing to memory and buffers. Although the current board is a prototype using an FPGA, the latency for 8 Bytes data transfer is only 0.441µs.
field programmable logic and applications | 2002
Naoyuki Izu; Tomonori Yokoyama; Junichiro Tsuchiya; Konosuke Watanabe; Hideharu Amano
A reconfigurable network interface called RHiNET/NI is developed for parallel processing with PCs distributed within one or more floors of a building. Two configurations: the HS (High Speed) configuration only with a high speed primitive and the DSM (Distributed Shared Memory) configuration which supports sophisticated primitives can be selected by the network requirements.
IEEE Transactions on Parallel and Distributed Systems | 2005
Michihiro Koibuchi; Konosuke Watanabe; Tomohiro Otsuka; Hideharu Amano
Applied Informatics | 2003
Tomohiro Otsuka; Konosuke Watanabe; Jun Ichiro Tsuchiya; Hiroshi Harada; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Hideharu Amano
The IEICE transactions on information and systems | 2007
Konosuke Watanabe; Tomohiro Otsuka; Hideharu Amano
IEICE Transactions on Information and Systems | 2003
Tomonori Yokoyama; Naoyuki Izu; Jun Ichiro Tsuchiya; Konosuke Watanabe; Hideharu Amano; Tomohiro Kudoh
Archive | 2005
Michihiro Koibuchi; Tomohiro Otsuka; Konosuke Watanabe; Hideharu Amano
Archive | 2004
Tomohiro Otsuka; Konosuke Watanabe; Akira Kitamura; Michihiro Koibuchi; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudo; Hideharu Amano
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National Institute of Advanced Industrial Science and Technology
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