Konrad Karczewski
Częstochowa University of Technology
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Publication
Featured researches published by Konrad Karczewski.
international conference on parallel processing | 2001
Tomasz Olas; Konrad Karczewski; Adam Tomas; Roman Wyrzykowski
ParallelNuscaS is an object-oriented package for parallel finite elemt modeling, developed at the Technical University of Czestochowa. This paper is devoted to the investigation of the package performance on the ACCORD cluster, which this year was built in the Institute of Mathematics and Computer Science of this University. At present, ACCORD contains 18 Pentium III 750 MHz processors, or 9 SMP nodes, connected both by the fast MYRINET networkand standard Fast Ethernet, as well as 8 SMP nodes with 16 AMD Athlon MP 1.2 GHZ processors. We discuss the implementation and performance of parallel FEM computations not only for the message-passing model of parallel programming, but also for the hybrid model, which is a mixture of multithreading inside SMP nodes and message passing between them.
international conference on parallel processing | 2003
Tomasz Olas; Roman Wyrzykowski; Adam Tomas; Konrad Karczewski
ParallelNuscaS is an object-oriented package for the parallel finite element modeling, developed at Czestochowa University of Technology. This paper is devoted to modeling the performance of the package on PC-clusters. Such modeling allows for analyzing and predicting the performance of this complex scientific application on different computing platforms. Because both uniprocessor and SMP nodes are considered, we investigate not only the message-passing model of parallel programming, but also the hybrid model, which is a mixture of multithreading inside SMP nodes and message passing between them.
parallel computing in electrical engineering | 2002
Tomasz Olas; Lukasz Lacinski; Konrad Karczewski; Adam Tomas; Roman Wyrzykowski
ParallelNuscaS is an object-oriented package for FEM modeling on clusters, developed at the Technical University of Czestochowa. This paper is devoted to the investigation of the influence of communication mechanisms used in the ACCORD cluster on performance of FEM computations. Last year this cluster was built in the Institute of Mathematics and Computer Science of this University At present, ACCORD contains 18 Pentium III 750 MHz processors, or 9 SMP nodes, connected both by the fast MYRINET network and standard Fast Ethernet, as well as 8 SMP nodes with 16 AMD Athlon MP 1.2 GHZ processors, connected only by the Fast Ethernet.
Knowledge and Data Management in GRIDs | 2007
Konrad Karczewski; Lukasz Kuczynski
Nowadays grid applications process large volumes of data. This creates the need for an effective data-management solutions. For the ClusteriX project the CDMS (ClusteriX Data Management System) is being developed. Analysis of user requirements and existing implementations of a Data Management System have been the foundations for its creation. Special attention has been paid to make the system user-friendly and efficient.
parallel computing | 2006
Jan Kwiatkowski; Marcin Pawlik; Gerard Frankowski; Kazimierz Balos; Roman Wyrzykowski; Konrad Karczewski
The increase of the speed of computer networks paired with the ubiquity of inexpensive, yet fast and generously equipped hardware offers many organizations an affordable way to increase the available processing power. Clusters, hyperclusters and even grids, not so long ago seen only in huge datacenters, can now be found helping many small organizations in solving their computational needs. Clusterix is a truly distributed national computing infrastructure with 12 sites (static Linux clusters) located across Poland. The computing power of Clusterix can be increased by connecting additional clusters. These clusters are called dynamic because it is assumed that they will be connected to the core infrastructure in a dynamic manner, using an automated procedure. In the paper we present the design foundation of the Cumulus grid deployed at Wroclaw University of Technology, together with the method for its integration as a dynamic component in the Clusterix grid.
Springer US | 2010
Roman Wyrzykowski; Jack J. Dongarra; Konrad Karczewski; Jerzy Waśniewski
Transistor size reduction and more aggressive power modes in HPC platforms make chip components more error prone. In this context, HPC applications can have a diverse level of tolerance to memory errors that may change the execution in different ways. As the tolerance to memory errors depends on write frequency and access patterns, different programming models may exhibit a different behavior in the rate of failures and alleviate the performance loss caused by the overhead of fault-tolerance mechanisms. In this paper, we explore how tolerant to memory errors are two main parallel programming models, messagepassing and shared memory: we perform a memory vulnerability analysis and also conduct error propagation experiments to observe the effect of memory errors through program flow. Our results show the need for soft error resiliency methods based on memory behavior of programs, and the evaluation of the tradeoffs between performance and reliability.
Lecture Notes in Computer Science | 2006
Lukasz Kuczynski; Konrad Karczewski; Roman Wyrzykowski
Archive | 2016
Ewa Deelman; Jack J. Dongarra; Konrad Karczewski; Jacek Kitowski; Kazimierz Wiatr; Roman Wyrzykowski
Archive | 2014
Roman Wyrzykowski; Jack J. Dongarra; Konrad Karczewski; Jerzy Wasniewski
parallel processing and applied mathematics | 2010
Roman Wyrzykowski; Jack J. Dongarra; Konrad Karczewski; Jerzy Wasniewski