Kazimierz Wiatr

Building a National Distributed e-Infrastructure–PL-Grid

PL-Grid: Foundations and Perspectives of National Computing Infrastructure. Integrating Various Grid Middleware Components and User Services into a Single Platform. Towards Professional Service Operations in Grids. New Capabilities in QosCosGrid Middleware for Advanced Job. Management, Advance Reservation and Co-allocation of Computing Resources - Quantum Chemistry Application Use Case Seamless Access to the PL-Grid e-Infrastructure Using UNICORE Middleware User-Oriented Provisioning of Secure Virtualized Infrastructure Flexible and Extendable Mechanism Enabling Secure Access to e-Infrastructures and Storage of Confidential Data for the GridSpace2 Virtual Laboratory. X Table of Contents SARA - System for Inventory and Static Security Control in a Grid Infrastructure. Security Best Practices: Applying Defense-in-Depth Strategy to Protect the NGI PL Automation of System Monitoring Based on Fuzzy Logic or Rules Comparison of Two Designed Approaches with Regard toComputational Infrastructures A Toolkit for Storage QoS Provisioning for Data-Intensive Applications Implementation of Service Level Management in PL-Grid Infrastructure. Highly Integrated Environment for Parallel Application Development Using QosCosGrid Middleware. User-Friendly Frameworks for Accessing Computational Resources Online Web-Based Science Gateway for Nanotechnology Research Scripting Language Extensions Offered by the GridSpace Experiment Platform Managing Entire Lifecycles of e-Science Applications in theGridSpace2 Virtual Laboratory - From Motivation through Idea to Operable Web-Accessible Environment Built on Top of PL-Grid e-Infrastructure. GridSpace2 Virtual Laboratory Case Study: Implementation of Algorithms for Quantitative Analysis of Grain Morphology in Self-assembled Hexagonal Lattices According to the Hillebrand Method.Examining Protein Folding Process Simulation and Searching for Common Structure Motifs in a Protein Family as Experiments in the GridSpace2 Virtual Laboratory. InSilicoLab - Managing Complexity of Chemistry Computations Ab Initio Molecular Dynamics Simulations of Ketocyanine Dyes in Organic Solvents.Polish Contribution to the Worldwide LHC Computing. PL-Grid e-Infrastructure for the Cherenkov Telescope Array Observatory. Training in the PL-Grid as Key Component to Attract Users to Grid e-Infrastructures. Dissemination Activities Conducted within the PL-Grid Project as a Successful Means of Promotion of Its Offer and Achievements.

Constant coefficient multiplication in FPGA structures

Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from twos-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.

Implementation of multipliers in FPGA structures

This paper studies different solutions for carrying out multiplication: a fully functional multiplier denoted as variable coefficient multiplier (VCM), constant coefficient multiplier (KCM) and self-configurable multiplier denoted as dynamic constant coefficient multiplier (DKCM). For FPGAs which can be easily reconfigured the choice between the VCM and KCM cannot be easily defined. Furthermore, the DKCM is an additional, middle-way between the KCM and VCM solution, as it offers shorter reprogramming time but occupies more area in comparison with the KCM. In FPGAs, the choice of the optimum multiplier involves three factors: area, propagation and reconfiguration time, which have been thoroughly studied and respective implementation results given. Furthermore, to speed-up implementation of multipliers a design-automated tool has been developed which generates optimum (for given input parameters), VHDL description of multipliers.

AES hardware implementation in FPGA for algorithm acceleration purpose

In this paper we investigate hardware implementation of AES-128 cipher standard on FPGA technology. In many network applications software implementations of cryptographic algorithms are slow and inefficient. To solve that problems custom architecture in reconfigurable hardware was proposed to speed up the performance and flexibility of Rijndael algorithm implementation. We aimed to achieve the maximum speed and efficiency of cipher process, therefore pipeline architecture of AES module was proposed. The investigations involved simulations and synthesis of VHDL code utilizing Virtex4 series of Xilinx.

Implementation image data convolutions operations in FPGA reconfigurable structures for real-time vision systems

In this paper different architectures for real time image constant coefficients convolutions are considered. Accordingly, look-up-table (LUT) based multiplication/convolution, LUT based distributed arithmetic (DA) convolution and multiplierless convolution (MC) implementations into FPGA structures has been investigated. In one result, the choice between these architectures depends on given coefficients values, however in most cases the MC preferable. Furthermore the change of coefficient values in real-time systems is also considered. This work is a contribution to worldwide intense research on developing reconfigurable and user dedicated custom computing machines (CCM).

PL-Grid: foundations and perspectives of national computing infrastructure

The Polish Grid Initiative commenced in 2009 as part of the PL-Grid project funded within the framework of the Innovative Economy Operational Programme. The main objective is to provision a persistent heterogeneous computational platform for the Polish scientific community with a unified interface, enabling easy access to the distributed large-scale computing infrastructure. The project establishes a countrywide computing platform which supports scientific research through integration of experimental data and results of advanced computer simulations carried out by geographically distributed computer infrastructure and teams. The solutions applied in setting up this e-infrastructure facilitate integration with other, similar platforms around the world. In this chapter the foundations of the PL-Grid architecture, a brief history of the project and its most important objectives are presented.

Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs

This paper presents implementation of the double precision exponential function. A novel table-based architecture, together with short Taylor expansion, provides low latency (30 clock cycles) which is comparable to 32-bit implementations. Low area consumption of a single exp()module (roughtly 4% of XC4LX200) allows implementation of several parallel modules on a single FPGAs. The exp() function was implemented on the SGI RASC platform, thus external memory interface limitation allowed only a twin module parallelism. Each module is capable of processing at speed of 200 MHz with max. error of 1 ulp, RMSE equals 0,62. This implementation aims primarily to meet quantum chemistrys huge and strict requirements of precision and speed.

FPGA Implementation of 64-Bit Exponential Function for HPC

Most presented implementations of the exponential function confine to the single precision format. Increasing data width to the double precision format requires a different approach. The presented novel architecture employs three independent Look-Up Tables (LUTs) together with a short Taylor expansion exp(x)ap1+times. Implementation results show that the double precision exp() function implementation achieves huge performance with satisfactory accuracy, latency and FPGA area consumption.

FPGA implementation of the dynamic Huffman Encoder

Abstract At first part of this paper, the architecture for quasi-static Huffman encoder is described which main part is Look-Up Table (LUT). In order to reduce the hardware requirements, the maximum length of the encoded word is limited. This reduces the compression ratio insignificantly which is proved in this paper. The dynamic encoding is achieved by a change of the LUT contents and hardware-software co-design approach. Consequently counting the input words statistics (histogram) and sorting the resultant histogram is implemented in hardware. The final calculation of the new LUT contents and controlling the whole system is achieved by the soft-processor Micro Blaze.

FPGA implementation of addition as a part of the convolution

Addition is a fundamental operation for the convolution (FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adders tree have been considered, e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: Multiplierless Multiplication, Look-Up Table based Multiplication, Distributed Arithmetic. Furthermore, optimization techniques: Exhaustive Search and Greedy Algorithm have been implemented, and as a result, the Greedy Algorithm is the best solution when time of computation is of great importance. Otherwise, the Exhaustive Search should be employed for the number of the addition inputs n/spl les/8. This paper is a part of the research on the AuToCon-Automated Tool for generating Convolution in FPGAs.