Konrad Mayer

Classification of coins using an eigenspace approach

We present a vision-based approach to coin classification which is able to discriminate between hundreds of different coin classes. The approach described is a multistage procedure. In the first stage a translationally and rotationally invariant description is computed. In a second stage an illumination-invariant eigenspace is selected and probabilities for coin classes are derived for the obverse and reverse sides of each coin. In the final stage coin class probabilities for both coin sides are combined through Bayesian fusion including a rejection mechanism. Correct decision into one of the 932 different coin classes and the rejection class, i.e., correct classification or rejection, was achieved for 93.23% of coins in a test sample containing 11,949 coins. False decisions, i.e., either false classification, false rejection or false acceptance, were obtained for 6.77% of the test coins.

High-speed template matching with point correlation in image pyramids

Matching of a reference template with an image is a computationally expensive job. Particularly in fast real-time applications, large images and search ranges led to serious implementation problems. Therefore a reduction of the template size achieved by the selection of an appropriate subtemplate which is used for point correlation (subtemplate matching) may significantly decrease computational cost. In this paper a modified algorithm of the subtemplate point selection is proposed and explored. With the additional use of image pyramids, we can reduce the computational costs even further. The algorithm starts with a coarse search grid in the top level of the image pyramid generated for the full intended resolution. The procedure continues until the lowest level of the pyramid, the original image, is reached. The computational costs of this algorithm part satisfy the requirement for on- line processing. The preparation of the subtemplate for the point correlation is carried out in off-line mode, i.e., there is no rigorous limit of computational costs. The technique that applies the point correlation to image template matching within the image pyramid concept is proposed and the results obtained are discussed. It is especially useful for fast real- time system implementation when a large number of template matchings are needed in the same image.

Fast real-time recognition and quality inspection of printed characters via point correlation

Some technical applications need a fast and reliable OCR for critical circumstances like low resolution and poor contrast. A concrete example is the real-time quality inspection system of Austrian banknotes. One requirement to the system is that it has to read two serial numbers on each banknote and to check if they are identical To solve the problem we have developed a novel method based an idea similar to pattern matching. However, instead of comparing entire images we use reduced sets of pixels, one for each different numeral. The detection is performed by matching these pixel sets with the corresponding pixels in the image being analyzed. We present an algorithm based on two cost functions that computes in a reasonable time the reduced pixel sets from a given set of image templates. The efficiency of our OCR has been increased considerably by introducing an appropriate set of image preprocessing operations. These are tailored especially to images with low resolution and poor contrast, bu they are simple enough to allow a fast real-time implementation. They can be seen as a normalization step that improves the image properties which are essential for pattern matching.

Novel development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing

Although the hardware platform is often seen as the most important element of real-time imaging systems, software optimization can also provide remarkable reduction of overall computational costs. The recommended code development flow for digital signal processors based on the TMS320C6000(TM) architecture usually involves three phases: development of C code, refinement of C code, and programming linear assembly code. Each step requires a different level of knowledge of processor internals. The developer is not directly involved in the automatic scheduling process. In some cases, however, this may result in unacceptable code performance. A better solution can be achieved by scheduling the assembly code by hand. Unfortunately, scheduling of software pipelines by hand not only requires expert skills but is also time consuming, and moreover, prone to errors. To overcome these drawbacks we have designed an innovative development tool - the Software Pipeline Optimization Tool (SPOT(TM)). The SPOT is based on visualization of the scheduled assembly code by a two-dimensional interactive schedule editor, which is equipped with feedback mechanisms deduced from analysis of data dependencies and resource allocation conflicts. The paper addresses optimization techniques available by the application of the SPOT. Furthermore, the benefit of the SPOT is documented by more than 20 optimized image processing algorithms.

Region based matching for print process identification

For quality inspection of security printing systems it is necessary to measure the displacement between printing processes. We present a new approach for region based matching of color images. Maximally stable extremal regions are extracted from image color channels and are the basis for matching. Binary template matching is performed between pairs of regions taken from the corresponding color channels of different images and a displacement vector is derived for each matching pair of regions. Clustering of measured displacements taken from sequences of sample images allows the estimation of the accuracy of printing processes and the alignment of printing processes. Results of an experimental application to banknote printing process inspection are given.

SIS-Stamp: an integrated inspection system for sheet prints in stamp printing application

Postal stamps with print defects are valuable collectables for philatelists. However, stamp printers strive to emit exclusively defect-free stamps. In order to achieve high quality of the production process, each sheet is inspected by especially trained staff. This kind of inspection is very flexible but it is tedious and leads to unstable and irreproducible results. Based on the experience in quality inspection, the ARC Seibersdorf Research Team set the goal to design an automated sheet inspection system (SIS), in which the front and rear side of the sheet are quality-inspected in a fully automatic mode using image processing methods. The print inspection covers each single stamp in the sheet and includes, among others, misalignments of the individual print phases and the perforation, detecting defects like smears, splashes and missing parts of the print. The features to be inspected, as well as the defect sensitivity, can be defined by a special setup program. The patented mechanical sheet transportation system separates the sheets, transports them to the inspection stations, and finally, stacks them in two trays for good and defective sheets. The prototype of the SIS-Stamp is installed in the Austrian State Printing Office (Osterreichische Staatsdruckerei, OSD) for final inspection of postal stamps and vouchers.

SPOT: development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing

Although the hardware platform is often seen as the most important element of real-time imaging systems, software optimization can also provide remarkable reduction of overall computational costs. The recommended code development flow for digital signal processors based on the TMS320C6000TM architecture usually involves three phases: development of C code, refinement of C code, and programming linear assembly code. Each step requires a different level of knowledge of processor internals. The developer is not directly involved in the automatic scheduling process. In some cases, however, this may result in unacceptable code performance. A better solution can be achieved by scheduling the assembly code by hand. Unfortunately, scheduling of software pipelines by hand not only requires expert skills but is also time consuming, and moreover, prone to errors. To overcome these drawbacks we have designed an innovative development tool--the Software Pipeline Optimization Tool (SPOTTM). The SPOT is based on visualization of the scheduled assembly code by a two-dimensional interactive schedule editor, which is equipped with feedback mechanisms deduced from analysis of data dependencies and resource allocation conflicts. The paper addresses optimization techniques available by the application of the SPOT. Furthermore, the benefit of the SPOT is documented by more than 20 optimized image processing algorithms.

High-performance camera module for fast quality inspection in industrial printing applications

Today, printing products which must meet highest quality standards, e.g., banknotes, stamps, or vouchers, are automatically checked by optical inspection systems. Typically, the examination of fine details of the print or security features demands images taken from various perspectives, with different spectral sensitivity (visible, infrared, ultraviolet), and with high resolution. Consequently, the inspection system is equipped with several cameras and has to cope with an enormous data rate to be processed in real-time. Hence, it is desirable to move image processing tasks into the camera to reduce the amount of data which has to be transferred to the (central) image processing system. The idea is to transfer relevant information only, i.e., features of the image instead of the raw image data from the sensor. These features are then further processed. In this paper a color line-scan camera for line rates up to 100 kHz is presented. The camera is based on a commercial CMOS (complementary metal oxide semiconductor) area image sensor and a field programmable gate array (FPGA). It implements extraction of image features which are well suited to detect print flaws like blotches of ink, color smears, splashes, spots and scratches. The camera design and several image processing methods implemented on the FPGA are described, including flat field correction, compensation of geometric distortions, color transformation, as well as decimation and neighborhood operations.

High-Performance Smart Cameras

This chapter describes a high performance smart linescan camera developed to be used in quality inspection systems for high grade printed matter. Such an inspection system has to meet many demanding requirements as very high inspection resolution (better than 100 m) at high production speeds (up to 20 m/s). A total data rate of several Gigabytes per second has to be processed continuously. Under consideration of reasonable system costs, the term high performance is related to the most critical design factors: resolution, speed, throughput, and inspection quality. The smart camera approach overcomes the bottleneck between high speed imager and remote image processing system. Powerful processing units like high end field programmable gate arrays and digital signal processors are integrated into the camera housing. Thereby, it enables outstanding quality inspection in terms of accuracy and economical feasibility. Architectural elements covered in this chapter include the multiple exposure method, which allows the design of high speed linescan cameras based on area scan images, high throughput image processing, high level image processing, as well as a fiberoptic-based 10 Gbit Ethernet used as camera interface. The chapter concludes with an outlook to future developments in the field of high performance smart cameras.

Design considerations for scalable high-performance vision systems embedded in industrial print inspection machines

This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results.