Herbert Nachtnebel

A Network Time Interface M-Module for Distributing GPS-Timeover LANs

This paper provides a comprehensive overview of our Network Time Interface (NTI) M-Module, which facilitates high-accuracy time distribution in LAN-based distributed real-time systems. Built around our custom UTCSU VLSI chip, it hosts all the hardware support required for interval-based external clock synchronization: A high-resolution state- and rate-adjustable clock, local accuracy intervals, interfaces to GPS receivers, and various timestamping features. Maximum network controller and CPU independence ensures that the available NTI prototype can be employed in virtually any COTS-based system with MA-Module interface. Our experimental evaluation shows that time distribution with μs-accuracy is possible even in Ethernet-based system architectures, provided that the available configuration parameters are suitably chosen to cope with the various hidden sources of timing uncertainty.

A smart capacitive angle sensor

This paper presents a smart capacitive angle sensor suited for automotive and industrial use. To comply with tough constraints of such applications in terms of environmental conditions, unit costs, and physical size, a fully integrated solution is mandatory. However, the limitations and capabilities of a single mixed-signal integrated circuit have considerable impact not only on the hardware architecture of the digital and analog system components, but also on the feasible measurement algorithm. A thorough investigation of all major nonlinear effects leads to an accurate system-level model of the sensor which is used to design a robust and reliable fully integrated sensor system capable of handling signal offset and amplitude variations. In addition, the proposed system recognizes and reacts on electromagnetic disturbances. Measurements taken from a final prototype comply with the simulation results.

A feasible noise estimation algorithm for resource-limited sensor systems

Fault tolerance and self-checking capabilities are key features of modern smart sensors, which often require the integration of additional signal processing facilities. In high-volume production areas such as automotive applications, however, optimized controllers are employed that typically have only limited computing resources. This paper examines several algorithms to assess the noise in a quasi-closed loop measurement channel under the assumption that the stimulus can be held constant during noise measurement. Starting from the definition of standard deviation, we propose several modifications and obtain an easy-to-implement algorithm relying entirely on addition and shift operations. Numerical experiments based on simulated and measured noise verify the practicability of the approach. The proposed algorithm has already been successfully implemented in a capacitive angular speed sensor system for automotive applications.

High-performance camera module for fast quality inspection in industrial printing applications

Today, printing products which must meet highest quality standards, e.g., banknotes, stamps, or vouchers, are automatically checked by optical inspection systems. Typically, the examination of fine details of the print or security features demands images taken from various perspectives, with different spectral sensitivity (visible, infrared, ultraviolet), and with high resolution. Consequently, the inspection system is equipped with several cameras and has to cope with an enormous data rate to be processed in real-time. Hence, it is desirable to move image processing tasks into the camera to reduce the amount of data which has to be transferred to the (central) image processing system. The idea is to transfer relevant information only, i.e., features of the image instead of the raw image data from the sensor. These features are then further processed. In this paper a color line-scan camera for line rates up to 100 kHz is presented. The camera is based on a commercial CMOS (complementary metal oxide semiconductor) area image sensor and a field programmable gate array (FPGA). It implements extraction of image features which are well suited to detect print flaws like blotches of ink, color smears, splashes, spots and scratches. The camera design and several image processing methods implemented on the FPGA are described, including flat field correction, compensation of geometric distortions, color transformation, as well as decimation and neighborhood operations.

Design considerations for scalable high-performance vision systems embedded in industrial print inspection machines

This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results.

Architecture for hardware driven image inspection based on FPGAs

Requirements for contemporary print inspection systems for industrial applications include, among others, high throughput, examination of fine details of the print, and inspection from various perspectives and different spectral sensitivity. Therefore, an optical inspection system for such tasks has to be equipped with several high-speed/high-resolution cameras, each acquiring hundreds of megabytes of data per second. This paper presents an inspection system which meets the given requirements by exploiting data parallelism and algorithmic parallelism. This is achieved by using complex field-programmable gate arrays (FPGA) for image processing. The scalable system consists of several processing modules, each representing a pair of a FPGA and a digital signal processor. The main chapters of the paper focus on the functionality implemented in the FPGA. The image processing algorithms include flat-field correction, lens distortion correction, image pyramid generation, neighborhood operations, a programmable arithmetic unit, and a geometry unit. Due to shortage of on-chip memory, a multi-port memory concept for buffering streams of data between off-chip and on-chip memories is used. Furthermore, performance measurements of the processing module are presented.

Experimental Evaluation of High-Accuracy Time Distribution in a COTS-Based Ethernet LAN

Abstract This paper reports on the experimental evaluation of the Network Time Interface (NTI) M-Module developed in the SynUTC-project at TU Vienna. Designed for COTS-based distributed systems, the NTI provides all hardware-related features for high-accuracy interval-based external clock synchronization, like a high-resolution rate- and state-adjustable clock, local accuracy intervals, interfaces to GPS receivers, and various timestamping features. The evaluation results show that the NTI enables GPS time distribution with μs-accuracy even in Ethernet-based systems. However, the available configuration parameters must be carefully chosen -and experimentally verified- in order to cope with the various hidden sources of timing uncertainty.

Dependability aspects in capacitive angular measurement systems

Todays smart sensors allow for the implementation of ample computing resources to improve their performance without increasing chip area and thus production costs significantly. What makes them more complex and at first sight less robust is in fact also a chance to improve their fault tolerance. In this paper we present a fault analysis for a capacitive angular sensor designed for automotive applications. Based on the assessment of potential faults and effects degrading the performance, we discuss constructive and operative measures and design decisions that have been taken to enhance the robustness of the system. A key component is a self-calibrating carrier frequency measurement principle, which is used to compensate common drift effects as well as to filter out electromagnetic disturbances. Electrical faults can be detected and lead to a fail stop behavior of the system. It is shown how these fault tolerance mechanisms are implemented in both a passive (i.e., by virtue of system design) and active way through appropriate data processing algorithms. The results of the case study are considered typical for capacitive sensors, but seem applicable also to similar problems.

Fault tolerant carrier frequency tracking for closed loop measurement systems

Carrier frequency based capacitance measurement is commonly used for measuring extremely small values of capacitive angle and distance sensors. If operated in a closed-loop system with a synchronous demodulator it offers significant advantages over conventional capacitance measurement methods. However, it is vulnerable to in-band disturbance signals. This drawback can only be overcome by selecting a different (undisturbed) carrier frequency. Fully integrated capacitive sensors without any means of external frequency reference are compulsory requirements for many industrial applications. These systems purely rely on an internal oscillator, which has to be digitally tunable to cope with temperature and process effects. We present a combined method for tuning the operating frequency to an external reference circuit (LC-filter) and at the same time detecting in-band noise signals.

Geometry unit for analysis of warped image features on programmable chips

Among many constraints applicable for embedded visions systems in industrial applications, desired processing performance is a determining factor of system costs. For technically and economically successful solutions, it is essential to match algorithms and architecture. High-end field programmable gate arrays open the perspective to vision systems on a programmable chip, leading to reduced size and higher performance. The architecture proposed in our previous publications in 2004 and 2006 is based on reusable building blocks. This paper continues with a particular building block for backward warping and interpolation of arbitrary shaped image regions, which can be used for many image processing tasks, including image statistics, projections, and template matching. The architecture is discussed and a typical application for template matching is presented. The suggested unit serves as universal basis for high-level image processing implemented on programmable chips, which enables a new generation of integrated high performance embedded vision systems maintaining reasonable system costs due to design reuse of basic units.