V.K. Semenov

RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems

Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology.<<ETX>>

Experimental study of the RSFQ logic elements

New elements of the rapid single flux quantum (RSFQ) logic family have been designed, fabricated, and tested. All-Nb 14-layer 5 mu m technology using externally shunted tunnel junctions with j/sub c/=500 A/cm/sup 2/, I/sub c/R/sub s/=300 mu V, and B/sub c/ >

Digital to analog conversion based on processing of the SFQ pulses

Two novel circuits of DC voltage multipliers have been designed, fabricated using a 3.5 mu m 1000 A/cm/sup 2/ niobium trilayer technology, and successfully tested at low frequencies. A novel primary digital-to-analog (D/A) converter based on the processing of single-flux-quantum (SFQ) pulses has been suggested. The performance of analog-to-digital (A/D) converters combined from such primary D/A converters and voltage multipliers is discussed.<<ETX>>

Transmission of single-flux-quantum pulses along superconducting microstrip lines

The authors analyzed, designed, and tested drivers and receivers which make it possible to connect distant circuits of the rapid single-flux-quantum (RSFQ) logic/memory family by passive superconducting microstrip lines. Using these circuits implemented with a niobium trilayer fabrication technology, reliable transmission and reception of the SFQ pulses over distances up to 1 cm, with margins of bias currents as wide as +or-30%, have been demonstrated. The pulses can be passed along wide lines (20 mu m for 3.5 mu Nb-Al/sub 2/O/sub 3/-Nb Josephson junction technology) over such distances and can be picked up by the RSFQ receiver.<<ETX>>

Josephson junction with lateral injection as a vortex transistor

Long narrow Josephson junctions with current injection to their long (lateral) sides are examined theoretically. Injection into a finite number of points as well as distributed injection are considered. The external magnetic field effect on the critical current and on the I-V curves is calculated. It is shown that the junction with current injection into many points in parallel is an almost complete analog of a conventional semiconductor transistor, the role of electric charge carriers being played by Josephson vortices carrying a single flux quanta. The use of a vortex transistor as a circuit element of both analog and digital devices is discussed.

4-bit rapid single-flux-quantum decoder

We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.<<ETX>>

Experimental realization of a resistive single flux quantum logic circuit

An integrated circuit including all basic components of the recently suggested Resistive Single Flux Quantum (RSFQ) logic family has been designed, fabricated and tested successfully. The circuit includes a generator of periodic SFQ pulses, four buffer/amplifier stages for splitting, channeling and regeneration of the pulses, a detector/load stage, and universal RSFQ logic gate (here performing the NOT function). The 10μm design rule circuit employs 13 active Nb - Al 2 O 3 - Nb Josephson junctions with the critical current density ∼ 0.5 kA/cm2. externally shunted by Mo resistors with R 1 Ohm. The shunting provided critical damping of the junctions ( \beta_{c}\lsim 1 ) and reasonable ( \sim 500 \mu V) I c R product. The circuit operation has been tested by measurement of dc voltages \bar{V}_{i} across various Josephson junctions as functions of the dc current through the pulse generator. Correct and stable operation of the circuit for the clock frequencies from 0 to ∼30 GHz has been demonstrated.

New elements of the RSFQ logic family

In this report, new rapid single-flux quantum (RSFQ) elements (OR-AND, NOR-AND, half adder, multiplexer, demultiplexer, and shift registers) are presented. Operation of these gates has been studied with the help of the personal superconductor circuit analyzer (PSCAN) within the standard RSJ model of Josephson junctions. Parameter margins and other performance limits of the new elements are thoroughly investigated.

Reversible conveyer computation in array of parametric quantrons

A possibility of physically and logically reversible processing of digital information in Josephson-junction circuits of a reasonable complexity has been considered. As example, a 8-bit 1024-point fast convolver has been designed on the basis of a two-dimentional quasi-uniform array of \sim 250\times30,000 parametric quantrons. This completely reversible conveyer device can operate with the estimated rate of at least \sim10^{9} numbers per second, which corresponds to \sim10^{14} binary logical operations per second. At this rate the power dissipation in the whole device can still be as low as ∼30nW. A new mode of the parametric quantron operation with larger parameter margins is also described.

Experimental implementation of analog-to-digital converter based on the reversible ripple counter

A new A/D converter which includes a comparator, and a reversible binary counter with DC outputs has been designed, fabricated, and tested. The comparator generates two trains of the single-flux-quantum (SFQ) pulses in response to increasing or decreasing input signal. The pulses are transferred through SFQ transmission lines to the adding and diminishing inputs of a reversible counter. The reversible counter has been realized by supplementing the usual counter with the SFQ transmission lines, splitters; and confluence elements for sending diminished pulses directly to each bit. Nondestructive read-out of the counter contents is carried out by SFQ/DC converters connected to each counter bit. The integrated circuit is fabricated using 5- mu m Nb-AlO/sub x/-Nb Josephson junction technology with a critical current density about 500 A/cm/sup 2/. External Mo shunts of the junctions provide the value of beta /sub c/<or=1 and I/sub c/R approximately=300 mu V. The A/D conversion is studied for low-frequency signals with an external clock. High-frequency performance of the reversible counter has been tested.