Konstantin Kholostov

New selective wet processing

A new selective processing technique based on a confined dynamic liquid drop\meniscus is presented. This approach is represented by the localized wet treatment of silicon wafers using dynamic liquid drop that while is in contact with the wafer forms a dynamic liquid meniscus. The main scientific innovation and relevance introduced by this work have been applied to industrial solar cell production and on silicon wafer metal bumps formation for the IC interconnection (i.e. copper pillars). Such new technique allows to touch in specific defined positions the silicon wafer in order to perform any kind of wet processing (e.g. etching, cleaning and/or plating) without the need of any protective resist. To investigate on pendant dynamic liquid drops and dynamic liquid meniscus use of computational fluid dynamic technique (i.e. numerical techniques to accurately predict fluid flows) was followed and is presented. An experimental setup has been built to validate the calculations. Numerical results showed a good agreement with experimental ones. Prototypes heads, using stereo-lithography systems, were developed and localized selective plating without the need of lithography step was performed on silicon.

Electroplated Nickel/Tin Solder Pads for Rear Metallization of Solar Cells

In this study, we report on the feasibility of formation of nickel/tin solder pads and bus bars directly electroplated onto the aluminum screen-printed rear metallization layer of silicon-based solar cells. A localized wet processing technique via dynamic liquid drop/meniscus is used to perform the electrodeposition procedure. Excellent mechanical and electrical parameters of electroplated contacts are measured, thus proving the reliability of the proposed approach suitable for industrial application. Adhesion of electroplated nickel/tin solder pads is ensured through a two-step electrochemical pretreatment procedure, resulting in mean peel force values ranging from 2.5 to 3.8 N/mm. Electroplating of solder pads directly onto the screen-printed aluminum layer allows us to obtain a full homogeneous back surface field on the solar cell, resulting in an efficiency gain in 0.31-0.48% abs range. Furthermore, the proposed method completely removes the need for silver in the rear-side metallization layer of silicon-based solar cells.

Porous silicon technology, a breakthrough for silicon photonics: From packaging to monolithic integration

Low cost concept based on the porous silicon technology is shown to be well suitable for integrating monolithically the photonic devices on a standard silicon wafers by using localized SOI structures fabricated by electrochemical anodization of silicon wafers followed by thermal oxidation of porous silicon. The new approach consists in realizing buried localized porous oxidized silicon by exploiting two different routes: n- epi/n+/n- structures on p-type wafers and ion-implantation on standard CMOS/BiCMOS wafers. The peculiarities of the developed approach, including anodization and thermal oxidation regimes to form oxidized porous silicon regions with the required properties are presented. The advantages of the proposed approach in realizing the fiber-to-chip and power-over-fiber coupling are discussed.

High uniformity and high speed copper pillar plating technique

In this work we report the application of the selective wet processing technique based on dynamic liquid meniscus for copper pillar bumps (CPB) plating. The industrial plating of copper for CPB process is typically carried out at 2 μm/min. A much higher copper deposition rate is necessary to improve throughput for this process. To achieve higher deposition rates of copper the hydrodynamic issue that is natural for all conventional plating baths processes must be solved. A number of solutions is proposed towards realization of high speed and high throughput CPB plating process. Uniformity of copper pillar over a 6-inches silicon wafer is presented and the morphology and shapes of pillars are investigated by scanning electron microscopy (SEM). Copper pillar height and dimension are investigated within different topology over the wafer showing the robustness of the process for the thickness uniformity. Preliminary investigation of the CPB plating shows the uniformity of better than 2 % within 6” silicon wafer.

Localized metal plating on aluminum back side PV cells

In this work we demonstrate a new selective metallization technique to perform localized plating on the screen-printed Al contact using the innovative approach based on Dynamic Liquid Drop/Meniscus that is able to touch the cell back contact in specific defined positions and show that it is possible to produce suitable electrical and mechanical contact with Al-Si and thus to replace the silver from the back contact in the cell manufacturing process reducing the solar cell cost. A fast pre-treatment process was developed to clean and prepare the surface of the aluminum on the back side of PV cells allowing direct plating with good electrical contact. Several commercial aluminum screen printable pastes have been experimented also having different distribution of sphere particles dimensions. We have used high resolution Scanning Electron Microscopy (SEM) and compositional microanalysis with Energy Dispersive X-Ray microanalysis (EDX) to evaluate the metal dispersion within aluminum-silicon inter-diffused region and Transfer Length Method and current-voltage measurements to estimate the specific contact resistivity of the metal contact and series resistance of the overall solar cell device. We have found that the interconnection ribbon soldered on tin contacts plated on screen printed aluminum back contact shows adhesion higher (> 1N/mm) than that verified on screen printed silver over silicon. The main difference between a tin pad and a nickel-tin pad will be shown. Efficiency increase and fill factor are compared respect standard Al-Ag back contact PV cell.

Electrochemically etched TSV for porous silicon interposer technologies

Silicon interposer technology offers System-In-Package (SiP) and System-On-Package (SoP) designers the unique possibility of achieving 3D integration without the need to implement Through-Silicon-Via (TSV) structures in active silicon, contributing to overall cost reduction of the final product. Silicon interposers require both horizontal and vertical interconnections, to redistribute the signals from the hosted chips. Vertical interconnections are achieved by TSV structures realized by Deep Reactive-Ion-Etching (DRIE) or LASER drilling processes. In this work is presented a lower cost alternative for realizing TSV on silicon wafers: electrochemical etching of silicon, forming vertical high aspect ratio macro-pores on the silicon wafer. The interposer itself is a macro-porous silicon layer, consisting of ordered, straight open pores at regular pitch. An optimized TSV fabrication process on low-cost (100)-oriented, p-type 10-20 Ωcm silicon wafers is presented. 100μm deep via with lateral diameter of 1.5μm and 2μm pitch have been achieved. In this work is reported the manufacture process, the achieved results.

Smart flexible planar electrodes for electrochemotherapy and biosensing

Electroporation is an effective method to deliver drugs into tumor cells to kill them, by applying a pulsed electric field to the cellular membrane. Existing electrodes consist of clamping claws or arrays of needles and can be effectively applied only to small areas. New electrodes that can treat large areas are sought; flexibility is needed to adapt to irregular tumor shape and, to be folded to enter from small surgical opening. In this work we present the design and test of a 16 cm2 flexible electrode for electroporation with biosensing capabilities, built with standard flexible circuit technologies enclosed in a biocompatible package. The electrode contains electronics to provide cryptography-based identification to the electroporation machine to avoid setup errors and protection against use of counterfeited electrodes. In-vitro tests of the electrode show that electroporation occurs up to a depth of 8 mm with 100% electroporation efficiency over the 30% of electrode area. Temperature rise on the electrode during treatment does not exceed 6 degrees celsius, a value that not causes damage to the cells.

Porous silicon solar cells

We developed a new process for the fabrication of crystalline solar cell, based on an ultrathin silicon membrane, taking advantage of porous silicon technology. The suggested architecture allows the costs reduction of silicon based solar cell reusing the same wafer to produce a great number of membranes. The architectures combines the efficiency of crystalline silicon solar cell, with the great absorption of porous silicon, and with a more efficient way to use the material. The new process faces the main challenge to achieve an effective and not expensive passivation of the porous silicon surface, in order to achieve an efficient photovoltaic device. At the same time the process suggests a smart way to selective doping of the macroporous silicon layers despite the through-going pores.

A new approach: Low cost masking material and efficient copper metallization for higher efficiency silicon solar cells

A new approach based on the development of a new low-cost masking material and a new technique for performing fast wet processes (i.e. chemical etching and electroplating processes) are presented, back side silver removal is proposed allowing in combination with a multi-bus bar module assembly technique to boost standard silicon solar cells towards higher efficiencies at low cost. The new masking material based on a low-cost wax is able to withstand wet hot chemical treatment up to 100 °C. The developed wax composition that costs 10 times less than photoresist can be taken into consideration as an industrial masking process for solar cell for the front copper metallization process. However, the industrial applicability of the copper plating processes foresees several issues concerning the cell throughput for the plating technique at industrial level, which is directly connected to the plating speed. In this work, it is shown how using the new concept of coalescent dynamic liquid drop/meniscus is possible to plate 35 μm thick copper fingers on wax masked solar cell with a deposition speed as high as 1 μm/s. Combining the proposed technique with the back side selective plating, a silver-free silicon solar cell fabrication process is developed allowing to reach efficiencies higher than 18 % for monocrystalline silicon solar cell.

3D Antenna for GHz application and vibration energy harvesting

In this work we present a new design for a three-dimensional vibration energy harvester, which is made by Micro-Electro-Mechanical Systems (MEMS) technology, and which can convert electric energy through transverse mode piezoelectric effect. The presented power generator is based on a long, thick-film, piezoelectric beam configured as a conical helix structure and located between two metal electrodes. The design of the combined antenna/energy harvester (comvester, from communication and energy harvester) device addresses both electromagnetic and mechanical issues as it radiates electromagnetic energy and converts mechanical energy into electric energy. Both functions are translated directly into dimensional constraints of the structure. In this work, we concentrate on millimeter waves communications in the 60 GHz frequency band because of their availability for low-power CMOS radio circuits. In order to realize comvester on a silicon wafer we used Controlled Release Metal Layer (CRML) technology, which is a transfer layer technology that uses porous silicon as sacrificial material. The advantage of CRML technology is high repeatability and resolution and its compatibility with back-end of line processes of the integrated circuit industry. New type of piezoelectric material consisted of the array of separated vertical polyvinylidene fluoride (PVDF) microrods is suggested. Such periodic microrods structure became possible to realize using the template of the structured macroporous silicon.