Konstantina Karagianni

A floating-point processor for fast and accurate sine/cosine evaluation

A VLSI architecture for fast and accurate floating-point sine/cosine evaluation is presented, combining floating-point and simple fixed-point arithmetic. The algorithm implemented by the architecture is based on second order polynomial interpolation within an approximation interval which is partitioned into regions of unequal length. The exploitation of certain properties of the trigonometric functions and of specific bit patterns that appear in the involved computations, has led to reduced memory size and low overall hardware complexity. In fact, a 40% memory size reduction is achieved by the introduced simplified memory interleaving scheme, when compared to a traditional interleaved memory architecture. The proposed architecture has been designed and simulated in a 0.7 /spl mu/m CMOS process technology, to prove its amenability for VLSI implementation. The time required to evaluate a sine is less than the time required for three single-precision floating-point multiply-accumulate (MAC) operations, while the computed values are guaranteed to be accurate to half a unit in last position. To prove the accuracy of the algorithm, an error analysis for the computation of the second-order Horner polynomial is provided, based on novel formulae which have been recently introduced in the literature by the authors for roundoff error bounds in floating-point addition and multiplication.

A low-complexity combinatorial RNS multiplier

A novel very large scale integration architecture and the corresponding design methodology for a combinatorial adder-based residue number system (RNS) multiplier are presented in this paper. The proposed approach to residue multiplier design, exploits the nonoccurring combinations of input bits to reduce the number of 1-bit full adders (FAs) required to compose an RNS multiplier. In particular, input bits which cannot be simultaneously asserted for any input residue value are organized into couples or triplets, which can be processed by OR gates instead of 1-bit adders, therefore reducing the RNS multiplier complexity. By comparing the performance and hardware complexity of the proposed residue multiplier to previously reported designs, it is found that the introduced architecture is more efficient in the area/spl times/time product sense. In fact, it is shown that a performance improvement in excess of 80% can be achieved in certain cases.

Digital baseband challenges for a 60GHz gigabit link

This paper presents the algorithms and corresponding hardware architectures developed in the context of the nexgen miliwave project, that compose the digital baseband processor of a 60GHz point-to-point link. The nexgen baseband processor provides all basic functionality required from a digital transmitter and receiver, including filtering, synchronization, equalization, and error correction. The techniques selected are capable of compensating impairments due to millimeter-wave front-end and yet support a throughput rate of more than one Gbp, with moderate hardware cost. As the nexgen link targets backhauling applications, a particularly low bit error rate specification of 10−12 has been adopted. Meeting the particular specification, as well as performance and complexity constraints, requires the adoption of sophisticated FEC techniques. Furthermore, extensive verification tasks need to be adopted which include hardware prototyping.

Operation-saving VLSI architectures for 3D geometrical transformations

Two VLSI architectures for the computationally efficient implementation of the elementary 3D geometrical transformations are introduced. The first one is based on a single floating-point multiply/add unit, while the other one comprises a four processing-element vector unit. By exploiting the structure of the elementary transformation matrices, some of the elements of which are ones and zeros, the proposed architectures avoid full-matrix multiplication for the matrix multiplications involved in the calculation of the transformation matrix by treating them as updates of specific elements, the new values of which are obtained by scalar operations in the case of the single-processor architecture or by simple vector operations in the case of the processor array. Thus, the floating-point operation count and the number of memory accesses required by a transformation are reduced and, therefore, the performance of the circuit which computes the transformation matrix, in terms of execution time, is improved at minimal hardware cost. Furthermore, a circuit is proposed which, for each sequence of transformations, selects the most appropriate direction for computing the product of the matrices in the corresponding stack of transformation matrices in order to further reduce the number of floating-point operations compared to the case where the direction of the computation of the successive matrix products is predetermined. The proposed single-processor architecture is suitable for low-cost applications, while the parallel execution scheme implemented by the introduced parallel processor may be implemented by any four-PE processor with small overhead.

A vector processor for 3-D geometrical transformations

A parallel VLSI architecture for the computationally efficient implementation of the elementary 3-D geometrical transformations is introduced. The trivial entries in the elementary transformation matrices are exploited, so that the matrix-matrix products required for the Transformation Matrix computation, are replaced by corresponding operations of the complexity of a vector operation. Acceleration of 68% to 84% per elementary transformation is achieved, at minimal hardware cost.

A Navier-Stokes processor for biomedical applications

VLSI implementation issues in the design of a parallel processor for the solution of a set of Navier-Stokes (NS) equations which model the flow of blood through a stenosis are discussed in this paper. Specifically, the Navier-Stokes equations and the Poisson equation are used for the calculation of the velocities and pressure of the blood in the stenosis. Selection of the stenosis model, definition of the computation grid, selection of the initial conditions and boundary conditions, discretization of the original equations, software simulations with the SIMPLER method are discussed. The impact of these choices on VLSI architecture complexity is investigated.

Efficient third-order Volterra filter computation in the time domain

This paper proposes a time-domain computational technique and a corresponding VLSI architecture for the hardware realization of Volterra kernels. By exploiting the symmetries in the algorithm, which stem from the commutative and associative properties of multiplication, a significant reduction of the number of required arithmetic operations is achieved. It is stressed that the proposed technique does not require that the Volterra kernel coefficient are symmetric.

Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems

The impact or a modified saturated arithmetic on power dissipation and signal quality produced by building blocks of a multicarrier modem is studied in this paper. The proposed simplified saturation scheme is shown to significantly reduce the switching activity of the arithmetic circuits, while it requires reduced hardware complexity for its implementation. Power estimation of synthesized circuits reveals power savings of up to 20%, depending on signal quality. The proposed saturation scheme is shown to moderately increase the power of noise, therefore leaving signal quality practically unaffected. The applicability of the proposed saturation is demonstrated by quantifying signal noise power behavior for various types of digital filters and radix-2 FFT structures suitable for OFDM modems

VLSI architectures for the implementation of the Wigner distribution

The Wigner distribution is a valuable tool for time-frequency signal analysis. Two different VLSI architectures for the real-time implementation of the Wigner distribution algorithm are proposed in this paper, with the objective of pointing out various computational issues that are involved. Reduction of the computational load of the algorithm, as well as reduction of the memory requirements has been achieved mostly by applying simple trigonometric properties to the original expression of the algorithm. The addressing schemes to access the memory blocks are also proposed.

A low-complexity RNS multiplier

Novel VLSI architectures and a design methodology for adder-based residue number system (RNS) multipliers are presented. In the proposed approach, the exploitation of the non-occurring combinations of input bits reduces the number of 1-bit full adders (FAs) required to compose a multiplier. In particular couples and triplets of input bits assigned to particular FAs are identified, which contain bits that cannot be simultaneously asserted for any valid input combination. It is shown that the particular couples or triplets can be assigned to OR gates instead of 1-bit adders, therefore reducing multiplier complexity. By comparing the performance and hardware complexity of the proposed multiplier to previously reported designs, it is found that the introduced architecture is more efficient in the area/spl times/time product sense. In fact, it is shown that more than 80% performance improvement can be achieved in certain cases.