Ahmed Mahdi

An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes

We consider the problem of rate-compatible (RC)-encoder and RC-puncturing of LDPC codes. The proposed encoder is based on a modification of MacKay encoding scheme. The introduced modification enables the application of MacKay scheme for quasi-cyclic (QC) LDPC codes combined with a proposed matrix puncturing scheme based on an also proposed parity-check matrix construction to achieve code-rate compatibility. The proposed encoding scheme and VLSI encoder architecture address the problem of encoding complexity, since about 80% of MacKay encoding algorithm complexity is linearly depended on LDPC check node degree. The proposed matrix puncturing scheme can produce good BER performance especially for high puncturing rates, where only a few parity check symbols are transmitted. A comparison with prior art in puncturing is offered, which shows superior performance of the proposed scheme, in terms of coding gain without any hardware cost.

Digital baseband challenges for a 60GHz gigabit link

This paper presents the algorithms and corresponding hardware architectures developed in the context of the nexgen miliwave project, that compose the digital baseband processor of a 60GHz point-to-point link. The nexgen baseband processor provides all basic functionality required from a digital transmitter and receiver, including filtering, synchronization, equalization, and error correction. The techniques selected are capable of compensating impairments due to millimeter-wave front-end and yet support a throughput rate of more than one Gbp, with moderate hardware cost. As the nexgen link targets backhauling applications, a particularly low bit error rate specification of 10−12 has been adopted. Meeting the particular specification, as well as performance and complexity constraints, requires the adoption of sophisticated FEC techniques. Furthermore, extensive verification tasks need to be adopted which include hardware prototyping.

Impact of LLR saturation and quantization on LDPC min-sum decoders

In this paper we quantify the power of noise due to quantization and saturation of the LLRs. Subsequently a model is constructed using the obtained noise power expressions that can be used to estimate the performance of various LLR quantization schemes. The model is validated by comparing the estimation with experimental BER results for an LDPC-based system that uses the min-sum layered decoding algorithm.

On the Encoding Complexity of Quasi-Cyclic LDPC Codes

In this paper, we propose a parity check matrix (PCM) construction technique that reduces the encoding complexity of quasi-cyclic (QC)-LDPC codes. The proposed construction method is based on a constraint selection of shifting factors, shown here to reduce the density of an inverted matrix used in several encoding algorithms. Furthermore, it demonstrates that the complexity of encoding schemes involving inverted matrices, can be defined by the density of the small inverted binary base matrix and not by the extended QC-PCM. Comparisons of the proposed codes with codes employed in international standards and with randomly shifted QC-LDPC codes of comparable characteristics, show the low complexity of the corresponding hardware implementations and a BER performance equivalent to that of previously reported codes without increasing the decoding complexity. Furthermore, adoption of the proposed method can decrease the complexity of several encoding procedures; in particular, an area reduction of 40%-55% is reported for QC-LDPC encoders, while a reduction of 86% is reported for Multi-Level-QC-LDPC encoders.

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems

This paper introduces a methodology for forward error correction (FEC) architectures prototyping, oriented to system verification and characterization. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations. FPGA devices give the designer the ability to observe rare events, due to tremendous speed-up of FEC operations. A Matlab-based system assists the investigation of the impact of very rare decoding failure events on the FEC system performance and the finding of solutions which aim to parameters optimization and BER performance improvement of LDPC codes in the error floor region. Furthermore, the development of an embedded system, which offers remote access to the system under test and verification process automation, is explored. The presented here prototyping approach exploits the high-processing speed of FPGA-based emulators and the observability and usability of software-based models.

A Low Complexity-High Throughput QC-LDPC Encoder

This paper introduces hardware architectures for encoding Quasi-Cyclic Low-Density Parity Check (QC-LDPC) codes. The proposed encoders are based on appropriate factorization and subsequent compression of involved matrices by means of a novel technique, which exploits features of recursively-constructed QC-LDPC codes. The particular approach derives to linear encoding time complexity and requires a constant number of clock cycles for the computation of parity bits for all the constructed codes of various lengths that stem from a common base matrix. The proposed architectures are flexible, as they are parameterized and can support multiple code rates and codes of different lengths simply by appropriate initialization of memories and determination of data bus widths. Implementation results show that the proposed encoding technique is more efficient for some LDPC codes than previously proposed solutions. Both serial and parallel architectures are proposed. Hardware instantiations of the proposed serial encoders demonstrate high throughput with low area complexity for code words of many thousand bits, achieving area reduction compared to prior art. Furthermore, parallelization is shown to efficiently support multi-Gbps solutions at the cost of moderate area increase. The proposed encoders are shown to outperform the current state-of-the-art in terms of throughput-area-ratio and area-time complexity by 10 to up to 80 times for codes of comparable error-correction strength.

Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders

In this paper we propose a parity check matrix construction technique that simplifies the hardware encoders for Multi-Level-Quasi-Cyclic (ML-QC) LDPC codes. The proposed construction method is based on semi-random - ML-QC extension and appropriately selects shifting factors to reduce the density of the inverted matrix used in several encoding algorithms. The construction method derives low-complexity encoders with minimal degradation of error-correction performance, observable at low BER only. Furthermore a VLSI encoding architecture based on the suggested parity-check matrix (PCM) is also introduced. Experimental results show that the complexity of the proposed encoders depends on the density of the binary base matrix. A comparison with random QC codes reveals substantial complexity reduction without performance degradation for cases of practical interest. In fact a hardware complexity reduction by a factor of 7.5 is achieved, combined with the acceleration of the encoder, for certain cases.

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs

Contemporary and next-generation wireless, wired and optical telecommunication systems rely on sophisticated forward error-correction (FEC) schemes to facilitate operation at particularly low Bit Error Rate (BER). The ever increasing demand for high information throughput rate, combined with requirements for moderate cost and low-power operation, renders the design of FEC systems a challenging task. The definition of the parity check matrix of an LDPC code is a crucial task as it defines both the computational complexity of the decoder and the error correction capabilities. However, the characterization of the corresponding code at low BER is a computationally intensive task that cannot be carried out with software simulation. We here demonstrate procedures that involve hardware acceleration to facilitate code design. In addition to code design, verification of operation at low BER requires strategies to prove correct operation of hardware, thus rendering FPGA prototyping a necessity. This paper demonstrates design techniques and verification strategies that allow proof of operation of a gigabit-rate FEC system at low BER, exploiting the state-of-the-art Virtex-7 technology. It is shown that by occupying up to 70% - 80% percent of slices on a Virtex-7 XC7V485T device, iterative decoding at gigabit rate can be verified.