Konstantinos Doris

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die [1] could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64× interleaved 2.6GS/s 10b 65nm CMOS ADC with on-chip calibrations, combining interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The ADC achieves an SNDR of 48.5dB at Nyquist and consumes only 0.48W.