A. Zanikopoulos

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and sampling linearity, while the back-end consists of four ADC arrays, each consisting of 16 10b current-mode non-binary SAR ADCs. The interleaving hierarchy allows for many ADCs to be used per T/H and eliminates distortion stemming from open loop buffers interfacing between the front-end and back-end. Startup on-chip calibration deals with offset and gain mismatches as well as DAC linearity. Measurements show that the prototype ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4 . An estimated sampling clock skew spread of 400 fs is achieved by careful design and layout. Up to 4 GHz an SNR of more than 49 dB has been measured, enabled by the less than 110 fs rms clock jitter. The ADC consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm.

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

Over the last years several low-power time-interleaved (TI) ADC designs in the 2.5-to-3.0GS/s range have been published [1-3], intended for integration in applications like radar, software-defined radio, full-spectrum cable modems, and multi-channel satellite reception. It is to be expected that future generations of these applications will require a higher ADC sampling rate, while maintaining good high-frequency linearity. Furthermore, a high spectral purity is desired, as spurs can cause an SNR degradation of several dB for weak narrowband signals. For interleaved converters, this mandates an output with limited interleaving artifacts. For the reception of broadband and multi-carrier signals, the gain mismatch and time-skew tones do not typically limit performance, since the spurs are evenly spread over frequency due to the broadband nature of the input signal. The offset mismatches, however, generate spurs at fixed frequencies, thereby representing the main performance limitation. This paper presents a prototype 3.6GS/s 11b TI SAR ADC with a THD that is better than -55dB at 2.5GHz and that has gain and offset spurs below -80dBFS, consuming 795mW in 65nm CMOS.

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die [1] could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64× interleaved 2.6GS/s 10b 65nm CMOS ADC with on-chip calibrations, combining interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The ADC achieves an SNDR of 48.5dB at Nyquist and consumes only 0.48W.

Smart AD and DA converters

In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance mixed-signal cores in VLSI chips. On the other hand, a trend of increasing digital processing power can be observed in almost all these systems. The presented smart approach takes full advantage of this trend in order to solve the before mentioned problems and to achieve true system integration.

Digital post-correction of front-end track-and-hold circuits in ADCs

This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique

Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs

This paper presents a method for the on-chip measurement and correction of gain errors, offsets and nonlinearities of a track-and-hold circuit (T&H) of an ADC. Open-loop T&H circuits were considered in this paper because of their high-speed and low-power capabilities. However, these open-loop circuits require calibration for the aforementioned errors in order to achieve a high accuracy, especially in case of time-interleaved architectures. With the proposed method, the errors can be measured and digitized on-chip accurately, without requiring a substantial amount of hardware or any accurate references. Then, this information is used by a digitally implemented algorithm to optimize several digitally controlled analog parameters of the circuit. In turn, these parameters minimize the effect of mismatch errors. After optimization, the digital logic can be switched off completely in order to save power.

A 62dB SFDR, 500MSPS, 15mW Open-Loop Track-and-Hold Circuit

In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals

This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.

Programmable/Reconfigurable ADCs For Multistandard Wireless Terminals

During the last years, there has been an evolution in wireless communication systems towards multifunction and multistandard terminals, supporting several standards, like GSM, Bluetooth, DECT, wireless LANs and UMTS. This paper presents the necessity to employ a fully programmable and reconfigurable (P/R) ADC in the implementation of multistandard terminals. Moreover, it explores the programmability and reconfigurability capabilities of ADC architectures, keeping focus on ADCs that are commonly used in telecom applications. We review and propose P/R ADC structures and we comment on their advantages and disadvantages

Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC

This paper presents the design procedure and performance of the basic building block of a flexible/modular pipelined ADC. We report the advantages of adopting a flexible ADC approach (Zanikopoulos et al., 2005) and we comment on the performance range that can be covered by this. Targeting a sampling frequency range from 50MS/s to 500MS/s and an accuracy range from 8b to 12b, we present and justify our design decisions leading to the implementation of the adjustable basic building block. The principle idea is the use of circuitries that can fully benefit from the speed-power consumption trade-off, while maintaining the desired accuracy. We employ dynamic circuitry and furthermore propose a fully adjustable open-loop amplifier suitable for flexible ADC realizations. Finally, we present the accuracy results and power consumption estimations along with the size of the building block implemented in a CMOS 0.18mum technology.