Kook Joo Lee

Radio-Frequency Electrical Characteristics of Single Layer Graphene

The radio-frequency (RF) electrical response of monolayer graphene is reported. From the measured S-parameter in the range of 10 MHz to 50 GHz, a simple equivalent resistor–inductor–capacitor (R–L–C) circuit is established to analyze frequency impedance. The impedance magnitude shows significant frequency dependence only below 10 GHz and this dispersive behavior is originated from the graphene–metal contact. Above 10 GHz, there is no distinctive change in overall characteristic of impedance due to the absence of the skin effect and low intrinsic kinetic inductance of graphene. These results show that graphene could be a promising candidate for high-speed device application.

A V-Band Waveguide Transition Design Appropriate for Monolithic Integration

V-band microstrip-to-waveguide transition design suitable for monolithic integration is presented. The transition size is minimized by using a dipole instead of a tapered slot. Integrating a single transition to the MMIC chip is expected to increases the total chip size by only 500 microns at 60 GHz. HFSS simulations show the transition possess 14 percent bandwidth for -10 dB mismatch loss. A dipole transition scale model was tested using X-band waveguide. The results showed the 10-dB mismatch bandwidth of 10 percent and the minimum insertion loss of 1.9 dB.

Parallel configuration of oscillator for strong harmonics suppression and frequency doubler

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are presented. In the oscillator design, as the fundamental signal is extracted between the dielectric resonator (DR) filter and the gate of the active device, the undesired harmonics at the output of the oscillator are remarkably suppressed. The fundamental signal of the oscillator directly feeds to the frequency doubler without an additional band pass filter to suppress spurious harmonics. The second harmonic suppression of -47.7 dBc at the single oscillator output and the fundamental suppression of -37.5 dBc at the frequency doubler output are achieved, respectably.

Millimeter-Wave CMOS On-Chip Dipole Antenna Design Optimization

This paper presents an optimized design of a millimeter-wave on-chip dipole antenna using CMOS process. The serious flaw of the antenna using CMOS process is low radiation efficiency because of high permittivity and conductivity. To overcome the weakness, we need to widen radiation area in air and optimize distance between an antenna and a reflector. The radiation efficiency and bandwidth of the designed antenna are respectively 16.5 % and 22.3 % at 80 GHz. Systematic methods are attempt to analyze an effect on the antenna radiation efficiency. To widen radiation area in air, substrate cut angle and distance between the antenna and chip edge are adjusted. In addition, to optimize distance between an antenna and reflector, substrate thickness and distance between the antenna and a circuit ground plane are adjusted.

A Wide-band Multi-layer Antenna Design using Double Resonance

In this paper, bandwidth enhanced design of dielectric resonator antenna fabricated in multi-layer substrate is introduced. The proposed dielectric resonator antenna is operating with fundamental TE101 mode and higher-order TM111 mode. Each resonance frequency is dependent on resonator dimensions. As increasing the height of radiating aperture, the higher-order TM111 mode resonance frequency approach the fundamental TE101 mode resonance frequency and the antenna bandwidth increase by double resonance. Three different aperture height size antennas that operated at 7GHz are fabricated in FR4 multi-layer substrate. Measured 10 dB matching bandwidth is 8 percent for single resonace antenna and 18 percent for double resonance antenna.