Kosei Okamoto
Toshiba
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Publication
Featured researches published by Kosei Okamoto.
international symposium on microarchitecture | 1988
Misao Miyata; Hidechika Kishigami; Kosei Okamoto; Shigeo Kamiya
The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japans TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second).<<ETX>>
ieee computer society international conference | 1988
Kosei Okamoto; Misao Miyata; Hidechika Kishigami; Takashi Miyamori; T. Sato
The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution units, and the ability to issue up to two instructions per cycle.<<ETX>>
Archive | 2003
Shinji Yamadaji; Mitsuaki Moritani; Kosei Okamoto; Hideyuki Toma
Archive | 2006
Kosei Okamoto; Hiroyuki Sakamoto; Akihisa Fujimoto; Masao Suga
Archive | 1989
Kosei Okamoto
Archive | 1991
Kosei Okamoto
Archive | 1988
Kosei Okamoto; Misao Miyata; Hidechika Kishigami; Takashi Miyamori; Tai Sat
Archive | 2012
Kosei Okamoto; Hiroyuki Sakamoto; Akihisa Fujimoto; Masao Suga
Archive | 2001
Kosei Okamoto; Hiroyuki Sakamoto; Akihisa Fujimoto; Masao Suga
Archive | 2001
Kosei Okamoto; Hiroyuki Sakamoto; Akihisa Fujimoto; Masao Suga
