Misao Miyata

The TX1 32-bit microprocessor: performance analysis, and debugging support

The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japans TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second).<<ETX>>

Experimental Polyprocessor System (EPOS)—architecture

The Experimental Polyprocessor System (EPOS) is described. It is a new computer system based on the concept of the polyprocessor and is intended to obtain a high degree of extensibility, cost/performance, adaptability and reliability. EPOS is composed of computing modules, input/output modules, and shared memory modules which are connected by multiple independent common buses. Modules and system buses can be added or deleted freely to provide a high degree of extensibility. The computing module is using a 7000-gate LSI computing element PULCE and provides extensive support for user and dynamic microprogramming. The input/output modules and the computing modules are connected equally to the system buses, and the same addressing mechanism is applied to them.

Design of a 32 bit microprocessor, TX1

Implementation of the TX1 VLSI microprocessor is described. Particular emphasis is placed on the design method, which meets the requirements of short design time with reasonable chip size. A one-phase clock system, which is a better solution for high-speed operation but requires careful design for evading the skew problem, is discussed. Design for testability is embedded in the chip. The TX1 is fabricated with a 1.0 mu m two-layer metal CMOS process. The chip contains 450 K transistors in a 10.89*10.27 mm/sup 2/ die. >

A one-day chip: an innovative IC construction approach using electrically reconfigurable logic VLSI with on-chip programmable interconnections

A new custom IC design methodology and the associated logic VLSI chip, which offer an ultimately fast turnaround-time logic IC construction method, are proposed. The chip contains various kinds of logic functional blocks, such as inverters, NORs, NANDs, flip-flops, shift registers, counters, adders, multiplexers, and ALUs. Up to 200 SSI/MSI standard logic blocks can be provided. The E/SUP 2/PROM-type MOSFET switch matrix is adjacent to the functional blocks, in order to connect any output to specific inputs of the functional blocks. It also offers a ready-to-test aid, obtained by monitoring the signal waveform developed inside the chip. These features have the advantage over the present custom IC design methods (gate array, standard cell, silicon compiler, programmable logic array) that the designer can easily redesign the logic to obtain a digital system in an IC in a single day.

The effectiveness of TRONCHIP instructions in the TX1 system

A description is given of the architecture of the TX1, which is the first 32-bit microprocessor of the Toshiba TX series. The TX1 supports 92 instructions including high-level instructions for efficient use of compilers and operating systems. The effectiveness of the high-level instructions was evaluated by comparing their execution cycles on the TX1 board computer with their equivalent programs using only basic instructions, and it was found that they could execute about two or four times as fast as the equivalent programs. About 27% performance improvement was achieved by using the high-level instructions in the Dhrystone benchmark program.<<ETX>>

Design considerations for 32-bit microprocessor TX3

The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution units, and the ability to issue up to two instructions per cycle.<<ETX>>