Kostas Doris

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and sampling linearity, while the back-end consists of four ADC arrays, each consisting of 16 10b current-mode non-binary SAR ADCs. The interleaving hierarchy allows for many ADCs to be used per T/H and eliminates distortion stemming from open loop buffers interfacing between the front-end and back-end. Startup on-chip calibration deals with offset and gain mismatches as well as DAC linearity. Measurements show that the prototype ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4 . An estimated sampling clock skew spread of 400 fs is achieved by careful design and layout. Up to 4 GHz an SNR of more than 49 dB has been measured, enabled by the less than 110 fs rms clock jitter. The ADC consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm.

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 μm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3 <; -83 dBc and NSD <; -163 dBm/Hz in the whole 100 MHz Nyquist band.

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

Over the last years several low-power time-interleaved (TI) ADC designs in the 2.5-to-3.0GS/s range have been published [1-3], intended for integration in applications like radar, software-defined radio, full-spectrum cable modems, and multi-channel satellite reception. It is to be expected that future generations of these applications will require a higher ADC sampling rate, while maintaining good high-frequency linearity. Furthermore, a high spectral purity is desired, as spurs can cause an SNR degradation of several dB for weak narrowband signals. For interleaved converters, this mandates an output with limited interleaving artifacts. For the reception of broadband and multi-carrier signals, the gain mismatch and time-skew tones do not typically limit performance, since the spurs are evenly spread over frequency due to the broadband nature of the input signal. The offset mismatches, however, generate spurs at fixed frequencies, thereby representing the main performance limitation. This paper presents a prototype 3.6GS/s 11b TI SAR ADC with a THD that is better than -55dB at 2.5GHz and that has gain and offset spurs below -80dBFS, consuming 795mW in 65nm CMOS.

Mismatch-based timing errors in current steering DACs

Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators.

A general analysis on the timing jitter in D/A converters

A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.

A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14µm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band.

A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS

This paper presents a 14 bit 35 MS/s successive approximation register (SAR) ADC that achieves a nearly constant 74.5 dB peak SNDR up to Nyquist and an SFDR of 90/99 dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sampling capacitor from the input and thereby eases the ADC drive requirements significantly. Since the buffers nonlinearity is cancelled by the SAR operation, a pair of basic source followers can be used, adding only 12.5 mW (23% of the total power) to the power budget. The ADC includes a bandgap reference and a self-calibrated current steering DAC to close the SAR loop, which eliminates the need for a low-impedance off-chip reference. The design occupies 0.236 mm 2 in 40 nm CMOS and consumes a total power of 54.5 mW from its 1.2/2.5 V supplies, leading to an SNDR-based Schreier FOM of 159.5 dB at Nyquist.

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

This paper presents a parallel sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals efficiently by exploiting the statistical properties of these signals. With this technique, the input signal power of an ADC can be boosted without getting excessive clipping distortion and the ADC can have a higher resolution over the critical small amplitude region. Hence the overall signal to noise and clipping distortion ratio is improved. This technique allows reducing power dissipation and area in comparison to conventional solutions for converting multi-carrier signals. As an example, an 11b switched-capacitor pipeline ADC with the parallel sampling technique applied to its first stage is implemented in CMOS 65 nm technology. It achieves a full-scale input signal range of 2 V differentially with a 1.2 V supply voltage. Simulations show an improvement of more than 5 dB in signal-to-noise-and-clipping-distortion ratio (SNCDR) and around 8 dB in dynamic range (DR) compared to a conventional 11b ADC for converting multi-carrier signals and achieve a comparable SNCDR and noise power ratio (NPR) as a conventional 12b pipeline for converting multi-carrier signals with less than half the power and area.

Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs

Timing errors become dominant in dynamic performance of high-speed and high-resolution current-steering digital-to-analog converters (DACs). To improve the dynamic performance and relax the requirements of timing errors in circuit/layout design, a mapping technique, based on on-chip timing error measurement, was proposed. This mapping technique can significantly improve the dynamic performance, no matter if timing errors are interconnection-related or mismatch-related. Matlab simulation results show that the spurious-free dynamic range (SFDR) is improved, e.g. 30dB for linearly distributed interconnection-related timing errors and 10dB for randomly distributed mismatch-related timing errors.

Smart AD and DA converters

In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance mixed-signal cores in VLSI chips. On the other hand, a trend of increasing digital processing power can be observed in almost all these systems. The presented smart approach takes full advantage of this trend in order to solve the before mentioned problems and to achieve true system integration.