J.A. Hegt

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer

Asynchronous sigma-delta modulators (ASDMs) are closed-loop nonlinear systems that transform the information in the amplitude of their input signal into time information in the output signal, without suffering from quantization noise such as in synchronous sigma-delta modulators. This is an important advantage with many interesting applications. In contrast with their synchronous counterparts, ASDMs have been underexposed. Both conceptually and analytically, they are quite complex. This paper investigates in detail the analysis, design and circuit-implementation aspects of ASDMs with a binary quantizer. In the ASDM, the amplitude-time transformation is done using an inherent self-oscillation denoted as a limit cycle. The oscillation frequency is addressed as the main design parameter that determines the spectral properties of the ASDMs and the quality of the amplitude-time transformation. Analytical and graphical derivations of the limit cycle frequency are treated. The impact of the filter order and the properties of the nonlinear element are elaborated on. Circuit implementations and the tradeoffs in the design are presented for a first- and a second-order ASDM that target the VDSL front-end specifications. Prototypes are implemented in a digital 0.18-/spl mu/m 1.8-V CMOS technology. The measured SFDR is 75dB in a frequency band of 8MHz for the first-order ASDM, and 72dB in a band of 12MHz for the second-order ASDM. The dissipated power is 1.5 mW and 2.2 mW, respectively.

A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.

Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch

This brief analytically investigates the digital-analog converter (DAC) integrated nonlinearity (INL) with respect to the accuracy of the DAC unit elements. The main novelty of the presented approach is in the application of the Brownian Bridge (BB) process to precisely describe the INL. This method analyzes the thermometer and binary DAC architectures and is the first to prove that their statistical INL properties are different. The INL of the thermometer DAC is represented as a one-dimensional BB process. For the binary case, the INL is represented as combinations of random variables, the increments of which coincide with a BB process. For both architectures, this brief derives formulas for the INL main statistical properties, e.g., probability density function, mean, deviation, and chip yield. These properties are compared with previous analytical attempts and conclusions are drawn. The results of this brief fill a gap in the general understanding of the most quoted DAC specification- the INL. In particular, for a high-volume chip production, the derived formulas will help engineers to choose the DAC architecture and the allowed mismatch of the DAC unit elements

A binary-to-thermometer decoder with built-in redundancy for improved DAC yield

This paper describes an architecture for binary-to-thermometer decoders used in segmented D/A converters. To improve basic converter characteristics, the architecture features redundant output thermometer code. The main concept offers two modes of operation. Each mode generates a different thermometer output, i.e. a different switching sequence for the DAC MSB thermometer analog elements. This results in two different transfer characteristics of the whole DAC for the same mismatch errors of its elements. After on-chip or off-chip measurements, the more linear transfer characteristic can be selected. In this way, chip yield is improved and the design requirements can be relaxed. Ultimately, the advantages introduced by the proposed decoder lead to cheaper and smaller D/A converters

A start-up calibration method for generic current-steering D/A converters with optimal area solution

This paper presents a new start-up calibration method for current-steering D/A converters, based on a 1-bit ADC. The paper proposes a new current cell that allows calibration of non-identical current sources by way of a shared calibration apparatus. The current cell uses parallel self-calibrated unit elements. Each of these is calibrated individually and when all combined together, the accuracy of the current sources is improved. This method is independent of the DAC architecture and hence an extra degree of design freedom exists. A minimal area solution can be found through optimizing the calibration strength, since the method is not only applicable to the identical thermometer current sources of the segmented DACs. A general discussion on the new calibration method is offered and conclusions are drawn.

Smart AD and DA conversion

List of symbols and abbreviations. 1. INTRODUCTION. 2. AD AND DA CONVERSION. 1 Introduction. 2 Trends in applications. 3 Trends in technology. 4 Trends in system design. 5 Performance criteria. 6 Conclusion. 3. SMART CONVERSION. 1 Introduction. 2 Smart concept. 3 Application of the smart concept. 4 Focus in this work. 5 Conclusion. 4. SMART DA CONVERSION. 1 Introduction. 2 Area of current-steering DACs. 3 Correction of mismatch errors. 4 Sub-binary variable-radix DAC. 5 Design example. 6 Conclusion. 5. DESIGN OF A SUB-BINARY VARIABLE-RADIX DAC. 1 Schematic design. 2 Layout. 3 Self-measurement-circuit implementation. 4 Experimental results. 5 Conclusion. 6. SMART AD CONVERSION. 1 Introduction. 2 Literature review. 3 High-speed high-resolution AD conversion. 4 Smart calibration. 5 Conclusion. 7. DESIGN OF AN OPEN-LOOP T&H CIRCUIT. 1 Literature review. 2 Design goal. 3 T&H architecture. 4 Sampling core architecture. 5 Output buffer architecture. 6 T&H design. 7 Experimental results. 8 Conclusion. 8. T&H CALIBRATION. 1 Introduction. 2 T&H accuracy. 3 T&H calibration method. 4 Analog correction parameters. 5 Digitally assisted analog correction. 6 Simulation results. 7 Implementation of the calibration method and layout. 8 Experimental results. 9 Conclusion. 9. T&H CALIBRATION FOR TIME-INTERLEAVED ADCS. 1 Introduction. 2 Channel matching in time-interleaved T&Hs. 3 Channel mismatch calibration. 4 Channel mismatch detection. 5 Channel mismatch correction. 6 Simulation results. 7 Implementation of the calibration method and layout. 8 Experimental results. 9 Conclusion. 10. CONCLUSIONS. References. Index.