Kostas Galanopoulos

Fast arbiters for on-chip network switches

The need for efficient implementation of simple crossbar schedulers has increased in the recent years due to the advent of on-chip interconnection networks that require low latency message delivery. The core function of any crossbar scheduler is arbitration that resolves conflicting requests for the same output. Since, the delay of the arbiters directly determine the operation speed of the scheduler, the design of faster arbiters is of paramount importance. In this paper, we present a new bit-level algorithm and new circuit techniques for the design of programmable priority arbiters that offer significantly more efficient implementations compared to already-known solutions. From the experimental results it is derived that the proposed circuits are more than 15% faster than the most efficient previous implementations, which under equal delay comparisons, translates to 40% less energy.

Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction

Direct all-digital frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital frequency synthesis cores, identifying their strengths and weaknesses.

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations for the bits of the leading-zero count are derived that allow their computation to be performed using standard carry-lookahead techniques. Using the proposed approach various design choices can be explored and different circuit topologies can be derived for the design of the leading-zero counting unit. The new circuits can be efficiently implemented either in static or in dynamic logic and require significantly less energy per operation compared to the already known architectures. The integration of the proposed leading-zero counter with the leading-zero anticipation logic is analyzed and the most efficient combination is identified. Finally, a simple yet efficient technique for handling the error of the leading-zero anticipation logic is also presented. The energy-delay behavior of the proposed circuits has been investigated using static and dynamic CMOS implementations in a 130-nm CMOS technology.

Merged Switch Allocation and Traversal in Network-on-Chip Switches

Large systems-on-chip (SoCs) and chip multiprocessors (CMPs), incorporating tens to hundreds of cores, create a significant integration challenge. Interconnecting a huge amount of architectural modules in an efficient manner, calls for scalable solutions that would offer both high throughput and low-latency communication. The switches are the basic building blocks of such interconnection networks and their design critically affects the performance of the whole system. So far, innovation in switch design relied mostly to architecture-level solutions that took for granted the characteristics of the main building blocks of the switch, such as the buffers, the routing logic, the arbiters, the crossbars multiplexers, and without any further modifications, tried to reorganize them in a more efficient way. Although such pure high-level design has produced highly efficient switches, the question of how much better the switch would be if better building blocks were available remains to be investigated. In this paper, we try to partially answer this question by explicitly targeting the design from scratch of new soft macros that can handle concurrently arbitration and multiplexing and can be parameterized with the number of inputs, the data width, and the priority selection policy. With the proposed macros, switch allocation, which employs either standard round robin or more sophisticated arbitration policies with significant network-throughput benefits, and switch traversal, can be performed simultaneously in the same cycle, while still offering energy-delay efficient implementations.

Optimal dithering sequences for spurs suppression in Pulse Direct Digital Synthesizers

Spurs-free frequency synthesis with minimal noise floor is achieved by the classical Pulse Direct Digital Synthesizers using a new class of dithering sequences with specific statistical properties. The generation of dithering sequences having statistical properties very close to those of the ideal ones with low-complexity architectures is also discussed and used to form All-Digital frequency synthesizers of minimal footprint and power consumption.

Sorter Based Permutation Units for Media-Enhanced Microprocessors

Single or multibit subword permutations are useful in many multimedia and cryptographic applications. Several specialized instructions have been proposed to handle the required data rearrangements. In this paper, we examine the hardware implementation of the powerful permutation instruction group (GRP). The design of the proposed permutation unit is based on the functionality of sorting networks. Two variants of the sorter-based GRP unit are introduced and analyzed and their energy-delay behavior is investigated using static CMOS implementations in a 130-nm CMOS technology.

Modulation techniques for all-digital transmitters based on Pulse Direct Digital synthesizers

Purely digital RF Transmitters of minimal footprint and power consumption and of acceptable performance for a wide range of applications are built out of Pulse Direct Digital frequency Synthesizers with spurs-suppression dithering and modulation capability. Several basic modulation schemes (FM/FSK/PM/PSK/AM/ASK) applied to Pulse Direct Digital frequency Synthesizers are considered.

Switch allocator for bufferless network-on-chip routers

Bufferless switches can be an attractive and energy-efficient design option for on-chip networks when network utilization is low and low-latency operation matters the most. However, this promising design option is limited by the complexity of the control logic required to operate a bufferless switch that imposes large delays and limits the clock frequency. Pipelining is not an option in this low-latency environment. In this paper, we propose a new switch allocator for bufferless switches that parallelizes the steps required for achieving a match between requesting inputs and available outputs and offers significantly faster implementations.

Predistortion of Digital RF PWM Signals Considering Conditional Memory

The trend in transmitter systems is to move the digital domain closer towards the antenna using digital modulators and drivers to reduce circuit complexity and to save power. A common assumption made is that they are capable of generating ideal pulses and thus do not suffer from analog imperfections. But the output signals of real drivers for high frequency operation are not perfectly rectangular anymore, which leads to distortion lowering the signal quality. In this paper the general properties of high frequency digital driver circuits operating at 2.6 GHz are analyzed and the impact of the different effects is presented. The predistortion of such drivers in the context of digital discrete time RF PWM modulators is studied. It has been found that conventional sample based predistortion can only correct the driver nonlinearity from -29 dBc to -49 dBc for the example considered using a 40 MHz bandwidth signal at 2.6 GHz. Therefore a special predistortion scheme considering the impact of pulses adjacent to the other samples is proposed. The mitigation of effects due to the discrete time nature of the signal is considered and discussed in detail. The capabilities of the proposed predistortion scheme are verified by extensive simulations as well as by measurements. By applying the proposed predistortion concept the spectral quality can be further improved to -66 dBc. In addition different scenarios with limited resolution and a carrier frequency offset are analyzed.

Delta-sigma modulation techniques to reduce noise and spurs in all-digital RF transmitters

This paper proposes a compact RF all-digital transmitter that is based on a direct digital synthesizer topology combined with Sigma-Delta modulation and other digital techniques to produce a spurs-free, high-frequency, single or few bit output with improved noise floor performance.