Kouichi Genda

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM

This paper describes a 320 Gb/s high-speed multichip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSIs are mounted on MCMs using the 150 /spl mu/m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput, which is applicable for future B-ISDN. >

A 160-Gb/s ATM switching system using an internal speed-up crossbar switch

A 160 Gb/s ATM switching system handling sixteen 10-Gb/s input lines is constructed by using an internal speed-up crossbar switch. The switch is structured around an input/output buffering switch architecture, high-speed bipolar devices and multichip module technology. The switch adopts a bufferless crossbar network realized with high-speed bipolar devices and cell buffers only on each input and output line. Using a separate architecture to link the bufferless routing network to the cell buffers, 20 Gb/s high-speed cell transmission can be easily realized in the crossbar network. In addition, a new high-speed arbitration algorithm using three bus lines on each output line, named the bi-directional arbiter, is adopted. The bi-directional arbiter is about 1.5 times faster than the conventional ring-arbiter and has the same fairness function. Using the switching system, a sub-tera-bit/s ATM switching system can be achieved in a significant step towards broadband ISDN.

TORUS: terabit-per-second ATM switching system architecture based on distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4/spl times/2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch.

Multichip module technologies for high-speed ATM switching systems

High-performance, compact multichip modules (MCMs) using a copper polyimide multi-layer substrate are used to make a 40-Gb/s-throughput ATM switching module. The MCM substrate has 392 high-speed signal I/0 channels, thin-film termination resistors, and 50 /spl mu/m laminated capacitance layers. We made a sub switching element module using these MCMs, new high-speed FPC cables, and heat pipes fins. This sub-switching element module can operate at 80 Gb/s throughput.

Multi-staged network restoration from massive failures considering transition risks

In a scenario of restoration from massive failures, a network is repaired through multiple restoration stages because availability of repair resources is limited. In a practical case, a network operator should assure the reachability of important traffic in transient stages, even as risks and/or operational overheads caused by stage transitions are suppressed. We discuss the novel problem of optimizing both traffic recovery ratio and transition risks caused by paths switching operation. We formulate our problem as linear programming, and show that it obtains Pareto-optimal solutions of traffic recovery versus transition risks. We also propose a heuristic algorithm for applying networks consisting of a few hundred nodes, and it could produce sub-optimal solutions within 4% difference from optimal solutions.

TORUS-switch: scalable Tb/s ATM switch architecture based on the internal speed-up ATM switch

An over 1 Tb/s scalable ATM switching system architecture is proposed suitable for the mature B-ISDN environment. Two kinds of switch modules are combined, the small-scale switch with VC and VP-level management named AHM having a 10 to 20 Gb/s throughput, and the high-speed and simple routing switch named AMC offering simple ATM layer management for AHMs-interconnection. The AMC resource management employs the grouped VP resource management scheme only at the AHM. The proposed system architecture gives a high statistical multiplexing gain from small-size switches to over 1 Tb/s switches and easy management; the switching capacity can be efficiently expanded. As the switch architecture of the AMC, a high-speed and scalable ATM switch architecture, named the TORUS-switch, is proposed. The switch is an internal speed-up crossbar-type switch with a cylindrical configuration. The self-bit-synchronization technique is adopted to achieve high-speed cell transmission without requiring high-density implementation technology. Also, a distributed contention-control based on the fixed output-precedence scheme is newly adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultra-high-speed crosspoint LSI using the advanced Si-bipolar process to confirm its feasibility. Measured results confirm that the TORUS-switch can be used to realize an expandable tera-bit-rate ATM switch that is also efficient.

Heat-Pipe Cooling Technology for High-Speed Atm Switching Mcms

This paper describes an innovative heat-pipe cooling technology for high-speed ATM switching MCMs operating with a throughput of 40 Gb/s. Although high-speed ATM link wires are interconnected on the top surface of the MCMs, there is no room to coot the MCM by forced air convection, because the power and the system clock signal are supplied by the connector on the back side and peripheral of the MCM. We therefore attach a cold-plate to the back of each MCM. The condenser parts of the heat pipe, which is mounted behind the power supply printed circuit board, are cooled by low-velocity forced air. Total power dissipation including the power dissipation of the termination resistors is about 30 watts per MCM. With a 2 m/s forced air flow, this sub-switching element module operates at a throughput of 80 Gb/s (including 4 MCMs) with maximum junction temperature of less than 85 /spl deg/C. Measured thermal resistance between the switch LSI junction and air is about 6 /spl deg/C/W at an air flow of 2 m/s. This heat-pipe cooling system has small system footprint, compact hardware, and good cooling capability. We, demonstrate its effectiveness in cooling high-speed ATM switching MCMS operating with a throughput of 40 Gb/s.

Crosspoint switch equipped with an interface for serial optical interconnection

A crosspoint switch was developed that has an interface for serial optical interconnection. By using optoelectronic devices, cascaded switching was achieved through serial optical interconnection up to a bit rate of 10 Gb/s.

Multi-stage network recovery considering traffic demand after a large-scale failure

When a massive network disruption occurs, repair of the damaged network takes time, and the recovery process involves multiple stages. We previously proposed a multi-stage network recovery method for determining the pareto-optimal recovery order of failed physical components, reflecting the balance requirement between maximizing the total amount of traffic on all logical paths, called total network flow, and providing adequate logical path flows to meet traffic demand. The pareto-optimal problem is formulated by mixed integer linear programming (MILP). In this paper, we propose a heuristic algorithm, called grouped-stage recovery (GSR), to solve the problem which cannot be solved with our previous method in a large-scale failure within a practical time. We numerically evaluated the effectiveness of our method with GSR. The results show that our method with GSR is applicable to large-scale failures because a nearly optimal recovery with less than 10% difference rate can be determined within practical computation time.

OSPF and BGP State Migration for Resource-Portable IP Router

This paper proposes an Internet protocol (IP) state migration method for developing resource-portable IP routers that are not virtual-machine based but commercial based. Resource-portable IP routers have the potential for achieving a sustainable network by functioning as a shared backup router. While previous studies relied on a virtualized technology (e.g., a virtual machine-based router on commodity hardware), current commercial routers was not virtualized but implemented as a proprietary hardware and software. We achieved IP state migration for a proprietary router with control packet sniffing of the open shortest path first (OSPF) protocol and border gateway protocol (BGP) peer masquerade using a software-defined network controller. We implemented our method and verified the accuracy of the state migration of routing tables generated using OSPF and BGP.