Yasuro Yamane

Characteristics including electron velocity overshoot for 0.1- mu m-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1- mu m-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n/sup +/-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length (a/L/sub g/). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n/sup +/-layers. The average electron velocity for 0.1- to 0.2- mu m-gate-length FETs is estimated to be 3*10/sup 6/ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f/sub T/ of 93.1 GHz has been attained by the 0.1- mu m SAINT MESFET. >

A 0.2 mu m GaAs MESFET technology for 10 Gb/s digital and analog ICs

A 0.2 mu m gate length GaAs IC technology is reported. This technology enables the fabrication of both digital and analog ICs using the same process. A 10 Gb/s decision circuit with a 130 mV sensitivity and 215 degrees phase margin, and an amplifier with a 20 dB gain and 13 GHz bandwidth were successfully fabricated using this unified process technology.<<ETX>>

A design technique for a high-gain, 10-GHz class-bandwidth GaAs MESFET amplifier IC module

A design procedure is proposed for a high-gain and wideband IC module, using stability analysis and a unified design methodology for ICs and packages. A multichip structure is developed using stability analysis and the requirements for stable operation are determined for each IC chip, package, and interface condition between them. Furthermore, to reduce the parasitic influences, several improvements in the interface and package design are clarified, such as wideband matching and LC resonance damping. IC design using effective feedback techniques for enlarging the bandwidth are also presented. The ICs are fabricated using 0.2- mu m GaAs MESFET IC technology. To verify the validity of these techniques, an equalizer IC module for 10-Gb/s optical communication systems was fabricated, achieving a gain of 36 dB and a bandwidth of 9 GHz. >

Extremely low-noise performance of GaAs MESFETs with wide-head T-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-/spl mu/m Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L/sub h/) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anholds method. A current gain cutoff frequency (f/sub T/) and a maximum stable gain (MSG) decrease monotonously as L/sub h/ increases on account of parasitic capacitance. However, the device with L/sub h/ of 1.0 /spl mu/m, which has lower gate resistance than 1.0 /spl Omega/, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMTs.

DC to 10-GHz mixer and amplifier GaAs IC's for coherent optical heterodyne receiver

The authors describe a number of design techniques that are effective for enhancing sensitivity and bandwidth. A Gilbert-cell circuit with a single-to-balance conversion input buffer and a peaking circuit are adopted for the mixer. In addition, a wideband amplifier is proposed that adopts a novel multiple-feedback cascode FET amplifier configuration with an LC input matching network. Finally, a novel interconnection technique is proposed that improves impedance matching between ICs and the package over a wide frequency range up to 10 GHz. These ICs were fabricated using a 0.2- mu m gate self-aligned GaAs MESFET process. These techniques could enable a highly sensitive multigigabit-per-second coherent optical heterodyne receiver to be implemented. >

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s

We developed a photoreceiver module for over 40 Gb/s that uses two ultrahigh- speed device technologies: an InP HEMT transimpedance amplifier (TIA) and a uni-traveling-carrier photodiode (UTC-PD). The TIA was designed to have a wide dynamic range by using cascade HEMT topology for the output buffer. We found that reducing the standing wave at the PD-TIA interface by decreasing the change of arg(S/sub 11/) of the TIA within the required frequency region is important for increasing the bandwidth of the module. We obtained a minimum sensitivity of -7.6 dBm and a dynamic range of 11 dB for 43-Gb/s nonreturn-to-zero optical input signal. Error-free operation of the module was confirmed at a data rate of 50 Gb/s.

Low-power InP-HEMT switch ICs integrating miniaturized 2/spl times/2 switches for 10-Gb/s systems

This paper presents a wideband cold-FET switch with virtually zero power dissipation. The use of InP HEMTs with a low R/sub on//spl middot/C/sub off/ product enables us to configure a DC-to-over-10-GHz single-pole double-throw (SPDT) switch without using a shunt FET. The series-FET configuration offers a logic-level-independent interface and makes possible positive control voltage operation in spite of using depletion-mode FETs. A miniaturized 2/spl times/2 switch using two SPDT switches yields an insertion loss of less than 1.16 dB and isolation of more than 21.2 dB below 10 GHz, which allows us to increase the scale of the switch in a single chip easily. The add-drop operation combining two 2/spl times/2 switches in a single chip and a 4/spl times/4 switch IC integrating four 2/spl times/2 switches are presented. The packaged ICs achieve error-free operation up to 12.5 Gb/s with either positive or negative logic-level input. Extremely fast switching of /spl sim/140 ps is also successfully demonstrated.

Depletion- and enhancement-mode modulation-doped field-effect transistors for ultrahigh-speed applications: an electrochemical fabrication technology

This paper is devoted to an electrochemical-etching-based technology for fabricating high-performance MODFETs for high-speed applications. The electrochemical etching in the gate openings is induced by the exposure of the Ni surface metal on the ohmic electrodes; it results in very slender gate-recess grooves, which are desirable for high-speed MODFETs because of the resulting achievable small gate-to-channel separation and low parasitic resistance. The technology is easy to implement, and is effective for enhancing the aspect ratio. Good control of aspect ratio is essential for achieving excellent device performance and limiting deleterious short channel effects. Successful vertical scaling, together with minimization of gate length by well-established electron-beam lithography using fullerene-incorporated electron-beam resist, leads to the realization of both optimal D- and E-mode MODFETs with ultrahigh extrinsic transconductance values and current gain cut-off frequencies. Fully passivated 0.07-/spl mu/m D-MODFETs with 2.25 S/mm extrinsic transconductance and current gain cut-off frequency exceeding 300 GHz have been successful fabricated. In addition, 0.03 /spl mu/m E-MODFETs with 2 S/mm transconductance and 300 GHz current gain cut-off frequency have been demonstrated. This electrochemical-etching-based technology provides both high-performance D- and E-MODFETs and, therefore, opens up the possibility to achieve ultrahigh-speed ICs based on DCFL configurations.

Bias acceleration model of drain resistance degradation in InP-based HEMTs

We formulated a lifetime of InP-based HEMTs in drain resistance increase using a bias E dependence model. Several bias accelerated tests at several bias points clarified that both an electric field and current density are necessary for a resistance increase in the drain side of a device. The obtained results suggest the degradation mechanism is that hot electrons created by impact ionization ionize impurities and those impurities are extracted by gate-drain electric field. The ionized impurities result in carrier donor passivation in the n-type InAlAs region and drain resistance increase. We reduced contamination in the fabrication process and thereby achieved long-lifetime HEMTs. In-addition, in a reliability study of 40 Gbit/s InP-HEMT ICs, a low operating voltage design was adopted and lifetime of over 1/spl times/10/sup 6/ h at 100/spl deg/C was obtained.

Frequency Dispersion in Drain Conductance of InAlAs/InGaAs Hight-Electron Mobility Transisters (HEMTs) and Its Relationship with Impact Ionization

We investigated the frequency dispersion in drain conductance of 0.1-µm-gate InAlAs/InGaAs high-electron mobility transisters under various bias conditions in a frequency range from 9 kHz to 500 MHz using a network analyzer. The substrate current was monitored from the backside of the wafer as a measure of the impact ionization rate. The relationship between the frequency dispersion and the impact ionization is explained quite well by the model we employed here. According to the model, the extrinsic transconductance of the device is the main factor governing the frequency dispersion of the drain conductance.