Kouichi Nagai

Correction method for high-precision CD measurements on electrostatically charged wafers

A correction method for automatic, high-precision CD-measurements on electrostatically charged wafers has been developed and installed in the Hitachi CD-SEM S-9260 to evaluate its performance. There are two types of charging: global and local. Global charging is stable and spreads all over a wafer while the local charging area is limited within the beam scanning area. A conventional CD-SEM has two weak points with respect to those charged wafers: one is failure at the positioning and autofocusing procedure which interferes with the fully automatic measurement sequence, and the other is disturbance of optical magnification which degrades the precision of CD-measurement values. By probing the global charging voltage with an electrostatic voltmeter prior to the CD-measurements, we subtract the voltage from a retarding voltage and then apply it to the wafer holder. The beam-focusing condition can stay within the fully automatically tunable range. And by generating numerical functions to represent the relationship between the global charging voltage, wafer height, excitation current of the objective lens and optical magnification, with the help of electron optical simulations, we can calculate the true optical magnification and the correct CD-measurement values. The local charging voltage is derived from the voltage shift of S-curves of secondary electron yield between conductive and insulated wafers measured with an energy filter. We correct the CD-measurement values using the simulated proportional relationship between magnifications of the electrostatic micro-lens and the local charging voltage. The coefficient is almost constant when the charging area is smaller than an equivalent circle of 100mm radius. We demonstrate that the CD-measurement values are successfully corrected within 0.1 percent in deviation for both charging types.

130-nm KrF lithography for DRAM production with 0.68-NA scanner

We have proposed a methodology for 130-nm DRAM patterning. We started by running a simulation to investigate the possibility of 130-nm DRAM production with KrF lithography. We optimized cell array features and isolate lines in the core circuits and peripheral circuits, corresponding to resist performance ((Delta) L). Using a half-tone phase-shift mask, off-axis illumination, and 0.68-NA KrF scanner, we found a high-performance resist of 40-nm (Delta) L that meets the requirement. Then, we screened resist samples using design of experiment. The result was a 40-nm (Delta) L positive resist that has small line edge roughness, a high- contrast resist profile, a small iso-dense bias and a low- blocking level to prevent defects. Finally, we applied this positive resist and OPC-mask to critical layers and achieved a sufficient production margin using a 0.68-NA KrF scanner.

Novel methodology for 130-nm DRAM cell mask size optimization

The possibility of 130-nm DRAM production with KrF lithography was investigated by simulation. First, the preferable exposure conditions that bring about sufficient exposure latitude (EL) for production were examined for each critical layer. Next, the effect of different mask errors of an attenuated phase shift mask on the EL was examined. In the experiments, a big difference was found on how much the errors reduced EL in the critical layers, and the EL of all patterns was found to change asymmetrically depending on the size comparison of completed mask and target design. In particular, if the contact hole size of Att. PSM is made smaller than design and exposure dosage becomes higher, EL decreases severely because of the sidelobe. As a result, selection of a size that is robust against mask errors instead of a size that exhibits the maximum exposure latitude without mask errors was found to maximize the practical EL in production. In this paper, we report on a novel methodology for 130-nm DRAM cell mask size optimization based on optical lithography simulation and dose-focus budget analyses. We also define the practical mask requirements for 130-nm DRAM production based on our simulation results.