Naoya Sashida

FRAM technologies compatible with 0.5-um CMOS logics

We developed FRAM (FRAM is a registered trademark of Ramtron International Corporation that stands for FeRAM) technologies that are fully compatible with half-micron CMOS logics. The technologies achieve 1T/1C FRAM cell 12.5 micrometer2 in a size and 68k-FRAM embedded 8bit-MCU. The CMOS transistors work at 5V for a cell operation and 3V for a logic operation. We did not use a COB to employ a present CMOS processing, and used the local interconnect to reduce a chip size. We used the W plug to contact to deep diffusion layers through high-aspect contact holes. The CMP planarization was used to relax PZT deposition and Pt etching. To prevent the process degradation of PZT, we used single Al wiring with SOG as an interlayer dielectric. The cover dielectric was formed with plasma TEOS- CVD without SiN to prevent the process degradation at this case. The SiN cover will be indispensable in real products. These technologies achieved a cell size 6.95 X 1.8 equals 12.5 (micrometer2) for 1T/1C and 4.2 X 6.5 equals 27.3(micrometer2) for 2T/2C that are the smallest cell size in FRAMs that do not use a COB structure and a poly-plug as a storage.

A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance

We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.