Naoki Kitai

PLL synthesizer with multi-programmable divider and multi-phase detector

Dividers in PLL frequency synthesizers are reduced by half with multi-programmable dividers by introducing the (N+1/2) one. It has faster lock-up time and no drawbacks. A multi-phase detector for higher loop gain is also introduced.

PLL frequency synthesizer with an auxiliary programmable divider

The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of programmable dividers. In order to achieve the increase in the gain of the programmable divider, we have proposed a new PLL frequency synthesizer with multi-programmable divider by which the gain is increased even when the same reference frequency and the same division ratio as usual are used. In this paper we propose a simple PLL frequency synthesizer with an auxiliary programmable divider which is suitable for LSI implementation. It will be shown by theoretical considerations and experimental results that a higher speed lock-up time can be achieved.

Dead-zone-less PLL frequency synthesizer by hybrid phase detectors

In this paper, in order to achieve the low phase noise in a PLL frequency synthesizer, we propose a new dead-zone-less PLL frequency synthesizer by hybrid phase detectors. We have developed the combination divider with (N+ 1/2 ) programmable divider and ( 1/2 ) fixed divider and the 90 degrees shift circuit and developed hybrid phase detectors method with both the exclusive-OR type phase detector and the normal frequency-phase detector. The former detector requires the two input signals with 50% duty factor and /spl pi//2 phase difference under the locked state. A (N+ 1/2 ) programmable divider with a ( 1/2 ) fixed divider and the 90/spl deg/ phase shifter are effectively employed to meet the above conditions. Both the simulation and experimental results show that the proposed synthesizer works successfully.

Performance improvement in a binary phase comparator type PLL frequency synthesizer

In a phase locked loop (PLL) frequency synthesizer with a binary phase comparator, ringing is hard to suppress. In this paper, we propose a PLL frequency synthesizer with a modified binary phase comparator which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.