Krishna Chakravadhanula

Capture power reduction using clock gating aware test generation

Scan-based manufacturing test of low power designs often exceeds the very tight functional constraints on average and instantaneous logic switching. The logic activity during the shift and launch-capture of test pattern data may lead to excessive power consumption and voltage droop. This paper focuses on the management of instantaneous power during the capture phase. By taking advantage of the existing clock gating circuitry and selectively holding the value of some scan flip-flops, switching activity during the capture cycles of a test can be reduced. The effectiveness of this technique is demonstrated on several industrial designs that show up to 30% (55%) reduction in instantaneous (average) capture switching.

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

This paper describes the challenges of testing low-power designs that use the commonly used multi-supply multi-voltage (MSMV) and power shut-off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.

SmartScan - Hierarchical test compression for pin-limited low power designs

IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.

Test Generation for State Retention Logic

As low power designs with multiple switchable power domains become more common, there is a need to ensure that the low power component structures in the design -such as isolation cells, state retention logic, and level shifters - are robustly tested during manufacturing test. This paper describes some of the challenges involved in testing low power components like state retention logic and proposes a novel method for testing them by cycling through the power modes of the chip to test their retention capability.

Efficient testing of hierarchical core-based SOCs

As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.

Low cost at-speed testing using On-Product Clock Generation compatible with test compression

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuits DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs

Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention flops, level shifters, power switches, etc., – that must be tested not only structurally but also addressing their behavior across multiple power modes. This paper describes the challenges in testing the key low power components and proposes novel solutions. The defective behavior of state retention logic is modeled to enable fault grading. ATPG modeling of defective behavior of isolation logic and level shifters is described for designs that support multiple supply voltages and power shutoff. The solutions are supported by experimental results on industrial designs.

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices

Summary form only given, as follows. The push for portable, battery-operated, and “cool-and-green” electronics has elevated power consumption as the defining metric of integrated circuit (IC) design. Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power-aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and lowpower test generation). Physically-aware low-power test techniques are also becoming important for accuracy and hot-spot minimization, especially for designs at 22nm and below. Furthermore, with power optimization and power management techniques becoming “de-facto” in almost all 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory. This tutorial is intended to provide an in-depth and up-to-date understanding of low-power IC testing covering (a) dimensions of power-aware testing, (b) methods for test power analysis and signoff, (c) techniques for controlling test power consumption and (d) test of power managed designs. Case-studies illustrating industrial design deployment practices and existing EDA vendor support will be outlined to illustrate capabilities and gaps in the state-of-the-art.

Test Strategies for Gated Clock Designs

One of the ways often used to design for low-power consumption during functional operation in CMOS devices is to gate off clocks to areas of logic not needed for the current state of operation. By gating off clocks to state elements that are known to not need updating, the dynamic switching current can be reduced compared with allowing state elements to update when you don’t care what they contain. When clocks are gated, some amount of DFT is necessary to ensure ATPG can be used to create meaningful tests. This chapter describes some of the DFT approaches that can be applied so ATPG can deal with gated clocks. In addition, this chapter explores ways in which functional clock gating may be exploited to help reduce power during test.

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures

This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.