Krzysztof Kuchcinski

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.

LEneS: task scheduling for low-energy systems using variable supply voltage processors

The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for Low-Energy Scheduling (LEneS) and compare it to two other scheduling methods. LEneS is based on a list-scheduling heuristic with dynamic recalculation of priorities, and assumes a given allocation and assignment of tasks to processors. Our approach minimizes the energy by choosing the best combination of supply voltages for each task running on its processor. The set of experiments we present shows that, using the LEneS approach, we can achieve up to 28% energy savings for the tightest deadlines, and up to 77% energy savings when these deadlines are relaxed by 50%.

Constraints-driven scheduling and resource assignment

This paper describes a new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system-level synthesis. It addresses assignment of resources for operations and tasks as well as their static, off-line scheduling. Different heterogeneous constraints are considered for these problems. These constraints can be grouped into two classes: problem-specific constraints and design-oriented constraints. They are uniformly modeled, in our approach, by finite domain (FD) constraints and solved using related constrained programming (CP) techniques. This provides a way to improve quality of final solutions. We have developed in Java a constraint solver engine, JaCoP (Java Constraint Programming), to evaluate this approach. This solver and a related framework make it possible to model different resource assignment and scheduling problems, and handle them uniformly. The JaCoP prototype system has been extensively evaluated on a number of HLS and system-level synthesis benchmarks. We have been able to obtain optimal results together with related proofs of optimality for all HLS scheduling benchmarks and for all explored design styles (except one functional pipeline design). Many system-level benchmarks can also be solved optimally. For large randomly generated task graphs, we have used heuristic search methods and obtained results that are 1--3% worse than lower bounds or optimal results. These experiments have proved the feasibility of the presented approach.

Scheduling of conditional process graphs for the synthesis of embedded systems

We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Automated transformation of algorithms into register-transfer level implementations

This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled. >

System synthesis with VHDL

Preface. Part I: Preliminaries. 1. Introduction. 2. VHDL. 3. High-Level Synthesis. 4. System- Level Synthesis. 5. Optimization Heuristics. Part II: Transformational Approach. 6. Transformational Design Basics. 7. Synthesis of Advanced Features. 8. Hardware/Software Partitioning. Part III: Advanced Issues. 9. Test Synthesis. 10. Low-Power Synthesis. Bibliography. Index.

An algorithm for partitioning of application specific systems

A simulated-annealing based algorithm to partition an application specific system into a set of modules is presented. The role of partitioning is to discover the structure implicit in the functional specification of the system so as to guide high level synthesis decisions in a design environment for digital systems consisting of hardware parts and possibly software components. The partitioning algorithm can also be used to partition the final or intermediate results of a high-level synthesis process into several physical blocks. Experimental results show that the approach produces better register-transfer designs with less global communications.<<ETX>>

Embedded system synthesis by timing constraints solving

The paper presents an approach to embedded system synthesis which minimizes a system cost while implementing given timing requirements. The embedded system is represented by a set of finite domain constraints defining different requirements on process timing, system resources and interprocess communication. The assignment of processes to processors and interprocess communications to buses as well as their scheduling are then defined as an optimization problem. A prototype system, based on constraint solving techniques, has been implemented in CHIP 5, the constraint logic programming system. Experimental results show that this approach can be efficiently used to define different system constraints and generate optimized system implementations.

Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming

This paper presents global high-level synthesis (HLS) approach which addresses the problem of synthesis of conditional behaviors under resource constraints. In proposed methodology, the conditional behaviors are represented by hierarchical conditional dependency graphs (HCDG) and synthesized using derived constraints programming (CP) models. Our synthesis methods exploit multicycle operations and chaining as well as conditional resource sharing and speculative execution at the same time. We assign both functional units and registers while making possible to conditionally share these components. These techniques are essential in HLS and the experiments carried out using the developed prototype system showed good performance of the synthesized designs and proved the feasibility of the presented approach.

A constructive algorithm for memory-aware task assignment and scheduling

This paper presents a constructive algorithm for memory-aware task assignment and scheduling, which is a part of the prototype system MATAS. The algorithm is well suited for image and video processing applications which have hard memory constraints as well as constraints on cost, execution time, and resource usage. Our algorithm takes into account code and data memory constraints together with the other constraints. It can create pipelined implementations. The algorithm finds a task assignment, a schedule, and data and code memory placement in memory. Infeasible solutions caused by memory fragmentation are avoided. The experiments show that our memory-aware algorithm reduces memory utilization comparing to greedy scheduling algorithm which has time minimization objective. Moreover, memory-aware algorithm is able to find task assignment and schedule when time minimization algorithm fails. MATAS can create pipelined implementations, therefore the design throughput is increased.