Flavius Gruian

Hard real-time scheduling for low-energy using stochastic data and DVS processors

Addresses scheduling for reduced energy of hard real-time tasks with fixed priorities assigned in a rate monotonic or deadline monotonic manner. The approach described can be exclusively implemented in the RTOS. It targets energy consumption reduction by using both on-line and off-line decisions, taken both at task level and at task-set level. We consider sets of independent tasks running on processors with dynamic voltage supplies (DVS). Taking into account the real behavior of a realtime system, which is often better than the worst case, our methods employ stochastic data to derive energy efficient schedules. The experimental results show that our approach achieves more important energy reductions than other policies from the same class.

LEneS: task scheduling for low-energy systems using variable supply voltage processors

The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for Low-Energy Scheduling (LEneS) and compare it to two other scheduling methods. LEneS is based on a list-scheduling heuristic with dynamic recalculation of priorities, and assumes a given allocation and assignment of tasks to processors. Our approach minimizes the energy by choosing the best combination of supply voltages for each task running on its processor. The set of experiments we present shows that, using the LEneS approach, we can achieve up to 28% energy savings for the tightest deadlines, and up to 77% energy savings when these deadlines are relaxed by 50%.

Hard Real-Time Scheduling for Low-Energy Using Stochastic Data and DVS Processors

Addresses scheduling for reduced energy of hard real-time tasks with fixed priorities assigned in a rate monotonic or deadline monotonic manner. The approach described can be exclusively implemented in the RTOS. It targets energy consumption reduction by using both on-line and off-line decisions, taken both at task level and at task-set level. We consider sets of independent tasks running on processors with dynamic voltage supplies (DVS). Taking into account the real behavior of a realtime system, which is often better than the worst case, our methods employ stochastic data to derive energy efficient schedules. The experimental results show that our approach achieves more important energy reductions than other policies from the same class.

System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors

This paper focuses on system-level design methods for low energy consumption in architectures employing variable-voltage processors. Two lowenergy design flows are introduced. The first, Speed-up and Stretch, is based on the performance vs. low-energy design trade-off. The second, Eye-on-Energy, is based on energy sensitive scheduling and assignment techniques. Both of the approaches presented in this paper use simulated annealing to generate task-toprocessor assignments. Also, both use list-scheduling based methods for scheduling. The set of experiments presented here characterize the newly introduced approaches, while giving an idea about the cost vs. low-energy and performance vs. low-energy design trade-offs a designer has to make.

The SystemJ approach to system-level design

In this paper, we propose a new system-level design language, called SystemJ. It extends Java with synchronous reactive features present in Esterel and asynchronous constructs suitable for modelling globally asynchronous locally synchronous systems. The strength of SystemJ comes from its ability to offer the data processing and encapsulation elegance of Java, Esterel-like reactivity and synchrony, and the asynchronous de-coupling of CSP all within the Java framework. Using standard Java environments, for specification and modelling, or specialised reactive embedded processors, for high performance implementation, the SystemJ design flow is extremely versatile. With the increasing attention that Java gets in embedded systems, SystemJ comes to address data and control, software and hardware, modelling and implementation in a unified manner

Designing a concurrent hardware garbage collector for small embedded systems

Today more and more functionality is packed into all kinds of embedded systems, making high-level languages, such as Java, increasingly attractive as implementation languages. However, certain aspects, essential to high-level languages are much harder to address in a low performance, small embedded system than on a desktop computer. One of these aspects is memory management with garbage collection. This paper describes the design process behind a concurrent, garbage collector unit (GCU), a coprocessor to the Java Optimised Processor. The GCU, targeting small embedded real-time applications, implements a mark-compact algorithm, extended with concurrency support, and tuned for improved performance.

BlueJEP: a flexible and high-performance Java embedded processor

This paper presents BLUEJEP, a novel Java embedded processor, developed using the relatively new Bluespec System Verilog (BSV) environment. The starting point for BLUEJEP is a micro-programmed, pipelined, Java-optimized processor (JOP), written in VHDL. Our BSV solution features a number of design choices, including a longer pipeline and speculative execution, that make the design more flexible, maintainable and high-performance. BLUEJEP also appears to be an excellent platform for exploring a number of Java specific techniques, both in hardware (bytecode folding, memory management, and caching strategies) and in software (runtime environment, bytecode optimizations). Tests and measurements were carried out both through simulation and on implementations running on a Xilinx FPGA.

Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time

Energy consumption reduction is today an important design issue for all kinds of digital systems. Offering both flexibility and efficient energy management, variable speed processor architectures are prefered for low energy consumption even in hard real-time systems. For this type of systems, the main approach consists in trading speed for lower energy while meeting all deadlines. For tasks with varying execution time, speed scheduling is most efficient if performed at run-time.This paper presents a new ordering technique for such tasks, that reduces the energy consumption resulting from the run-time speed scheduling. Without affecting the real-time behavior, our Uncertainty-Based Scheduling (ubs) is a low complexity but energy-efficient method that can be applied on top of already existent real-time scheduling techniques, such as edf. These claims are backed up by extensive simulation results accompanied by measurements on a platform based on an Intel i80200 XScale processor.

Low-energy directed architecture selection and task scheduling for system-level design

Most of the current methods for designing power/energy efficient digital systems are addressing either the system hardware or system software. This is usually performed quite late in the design process. This paper presents a method for minimizing the energy consumption at system level, early in the design process. Our approach to low-energy system design uses constraint programing to achieve this goal. Considering a system composed of several communicating tasks running on a multiprocessor architecture, our method tries to find for a given deadline, the best schedule and configuration of processors from the energy consumption point of view. Finally, we present a set of experiments which confirm the importance of addressing the energy consumption at system level.

Automatic generation of application-specific systems based on a micro-programmed Java core

This paper describes a co-design based approach for automatic generation of application specific systems, suitable for FPGA-centric embedded applications. The approach augments a processor core with hardware accelerators extracted automatically from a high-level specification (Java) of the application, to obtain a custom system, optimised for the target application. We advocate herein the use of a microprogrammed core as the basis for system generation in order to hide the hardware access operations in the micro-code, while conserving the core data-path (and clock frequency). To prove the feasibility of our approach, we also present an implementation based on a modified version of the Java Optimized Processor soft core on a Xilinx Virtex-II FPGA.