Krzysztof S. Berezowski

Identification of Threshold Functions and Synthesis of Threshold Networks

This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This methods success depends on the ordering of the variables in the binary decision diagram (BDD). An alternative data structure, and one that is more compact than a BDD, called a max literal factor tree (MLFT) is introduced. An MLFT is a particular type of factoring tree and was found to be more efficient than a BDD for identifying threshold functions. The threshold identification procedure is applied to the MCNC benchmark circuits to synthesize threshold gate networks.

Exploiting residue number system for power-efficient digital signal processing in embedded processors

2s complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propagation. Residue Number System (RNS) breaks free of these bonds by decomposing a number into parts and performing arithmetic operations in parallel, significantly reducing the breadth of carry propagation. Consequently, RNS arithmetic has been proposed as a solution to improve the power-efficiency of arithmetic hardware. However, limitations of the expressiveness of RNS in terms of arithmetic operations together with overheads related to interaction with 2s complement arithmetic make programmable processor design that takes advantage of these benefits challenging. In this paper we meet this challenge by multi-tier synergistic co-design of architecture, micro-architecture, hardware components, as well as compilation techniques. Our experiments not only demonstrate simultaneous improvement of up to 30% in performance and 57% reduction in functional unit power consumption, but also that most of these benefits can be exploited with automatically generated code.

Fast and energy-efficient constant-coefficient FIR filters using residue number system

In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques of sharing of subexpressions in the multiplier block (MB), to its optimized usage in the MB and accumulation pipeline hardware design. As a result, we propose a common subexpression elimination (CSE) based synthesis technique for RNS-based MBs, along with a high-performance RNS-based FIR filter architecture that employs RNS arithmetic principles but implements them mainly using more efficient 2s complement hardware. Several filters with numbers of taps ranging from 25 to 326 and dynamic ranges from 24 to 50 bits have been synthesized using TSMC 90 nm LP kit and Cadence RTL Compiler. Comparison of power, delay, and area of the new filters implemented using the 4- and 5-moduli RNSs against various equivalent 2s complement counterparts show uniform improvement in performance and power efficiency, often accompanied by significant reduction in area/power consumption as compared to 2s complement implementations. We observed up to 22% improvement in peformance (19% reduction in area) within bounded power envelope, or up to 14% reduction in power consumption (12% reduction in area) at same frequency.

Design of a robust, high performance standard cell threshold logic family for DSM technology

This paper presents the threshold logic latch (TLL), which provides a high performance, low power alternative to traditional CMOS logic networks. TLL is highly robust, even in deep sub-micron technology nodes. Experimental results obtained from simulation of a commercial 65 nm low power process demonstrate a static noise margin up to an order of magnitude greater than those of existing implementations of threshold logic. Examples of automated synthesis of pipelined multipliers using a combination of standard CMOS and a small number of TLL gates are shown through simulation to improve both area and total power by a factor of up to 1.5 and reduce leakage power by a factor of up to 2.3.

Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices

In this paper, we present a novel multiple-valued logic circuit design style based on negative differential resistance (NDR) devices and the mono stable-to-multistable transition logic (MML) operating principle. We introduce an innovative topology that considerably enhances the design space of MML circuits thus providing more functionality achievable within an atomic multiple-valued circuit. The functional correctness of the design is proved by simulations.

Toolset for measuring thermal behavior of FPGA devices

In this work, we present a toolset suitable for the analysis of thermal behavior of FPGA devices. The toolset allows for the automatic synthesis of a unified temperature measurement and heat generation infrastructure combined with the necessary control structures and communication interfaces. The tools insert temperature sensors and heaters based on ring oscillators through the low level manipulations on Xilinx Design Language descriptions of FPGA resource allocations. The purpose of the kit is to support rapid setup of thermal experiments by providing basic heating and sensing elements with verified properties as well as an area-optimised IP core for control of the experiments.

Analytical results for design space exploration of multi-core processors employing thread migration

Migrating threads away from the hot cores in a multicore processor allows them to operate at up to higher speeds. While this technique has already attracted a lot of research effort, the majority of thread migration studies are simulation-based. Although they are valuable for micro-architectural level optimization, they require prohibitively long simulation times, and hence have limited value for early design space exploration. We derive closed form expressions for the steady-state throughput of a multicore processor that employs thread migration and throttling for thermal management. These expressions can be evaluated under a millisecond (vs days for cycle-accurate simulation), and allow designers greater flexibility in evaluating the trade-offs involved in implementing thread migration on-chip. We also developed a system-level power/thermal simulator that we used to validate the analytical results.

Automatic design of binary and multiple-valued logic gates on RTD series

In this paper, we contribute to the binary and multiple-valued applications of resonant tunneling devices (RTDs). We propose a method of systematic design of physical parameters of RTD based logic. From the abstraction of their behavior, we model the design space as a handful of systems of linear inequalities generated for a given circuit topology and an arbitrary logic function. Any valid solution reflects the physical parameters assignment that implements the function given. We solve these systems using off-the-shelf optimization tool and verify the results using SystemC based RTD circuit model. Our simulations confirm that the numerical solutions are valid parameter assignments.

Transistor chaining with integrated dynamic folding for 1-D leaf cell synthesis

In this paper, a new method of transistor chaining for 1-D automatic leaf cell synthesis is presented. The method allows synthesis of cells suitable for row-based layouts with no restrictions imposed on network topologies/transistor sizes. The novelty of the solution arises from transistor chaining with integrated dynamic transistor folding. We provide the theoretical analysis of transistor folding, then formulate the problem and solve it using the computational model made after that of Bar-Yehuda et al. (1989). The model serves us as a basis for the novel algorithm constructed using the dynamic programming technique. The preliminary experiments show that the method reaches good quality chainings and the dynamic folding leads to further elimination of the diffusion gaps comparing to the recent results of other researchers. This results in the reduction of the layout width as well as the improvement of its manufacturability and quality.

Calibration of RO-based temperature sensors for a toolset for measuring thermal behavior of FPGA devices

In this work, we present a toolset suitable for the analysis of thermal behavior of FPGA devices. The toolset allows for the automatic synthesis of a unified temperature measurement and heat generation infrastructure combined with the necessary control structures and communication interfaces. The tools insert temperature sensors and heaters based on ring oscillators through the low level manipulations on Xilinx Design Language descriptions of FPGA resource allocations. The purpose of the kit is to support rapid setup of thermal experiments by providing basic heating and sensing elements with verified properties as well as an area-optimised IP core for control of the experiments.