Janusz Biernat

Fast and energy-efficient constant-coefficient FIR filters using residue number system

In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques of sharing of subexpressions in the multiplier block (MB), to its optimized usage in the MB and accumulation pipeline hardware design. As a result, we propose a common subexpression elimination (CSE) based synthesis technique for RNS-based MBs, along with a high-performance RNS-based FIR filter architecture that employs RNS arithmetic principles but implements them mainly using more efficient 2s complement hardware. Several filters with numbers of taps ranging from 25 to 326 and dynamic ranges from 24 to 50 bits have been synthesized using TSMC 90 nm LP kit and Cadence RTL Compiler. Comparison of power, delay, and area of the new filters implemented using the 4- and 5-moduli RNSs against various equivalent 2s complement counterparts show uniform improvement in performance and power efficiency, often accompanied by significant reduction in area/power consumption as compared to 2s complement implementations. We observed up to 22% improvement in peformance (19% reduction in area) within bounded power envelope, or up to 14% reduction in power consumption (12% reduction in area) at same frequency.

Fast fault-tolerant adders

Several measures can be undertaken to achieve fault-tolerance of arithmetic devices. They differ in the level of hardware redundancy and the coverage of detectable faults. The discussion of the possible solutions for fast fault tolerant adders is given in the paper. The hardware complexity growth and latency overhead of various designs with respect to fault-coverage is discussed in the paper. It is shown that the designs of fast fault-tolerant adders based on the concept of residue code or double-rail code are preferable.

Fault cryptanalysis of elgamal signature scheme

In this paper we examine the immunity of ElGamal signature scheme and its variants against fault cryptanalysis. Although such schemes have been already widely adopted, their resistance against fault cryptanalysis has not been verified in detail yet. However, at least some of them are not immune to fault cryptanalysis and can be broken without solving discrete logarithm problem. We will show that the selected signature schemes can be broken in O(nlog2n) steps if single bit-flip errors are inducted during computations. We also present two modifications that can be used to improve security of ElGamal scheme.

Design of an RNS reverse converter for a new five-moduli special set

In this paper, we present a new residue number system (RNS) {2^<i>n</i>-1, 2<i>n</i>, 2^<i>n</i>+1, 2^<i>n</i>+1+1, 2^<i>n</i>-1+1} of five well-balanced moduli that are co-prime for odd n. This new RNS complements the 5-moduli RNS system proposed before for even <i>n</i> {2^<i>n</i>-1, 2^<i>n</i>, 2^<i>n</i>+1, 2^<i>n</i>+1-1, 2^<i>n</i>-1-1}. With the new set, we also present a novel approach to designing multi-moduli reverse converters that focuses strongly on critical path analysis and aims at strongly on moving a significant amount of computations off the critical path. The synthesis of the resulting design over the ST Microelectronics 65nm LP library demonstrates that the delay, area, and power characteristics improve the performance and power consumption of the existing complementary 5-moduli set.

The alternate approach to the reliability modeling of fault masking systems

Abstract A new approach to the reliability modeling of fault masking systems is presented. In contrast to the models known in the literature the new model of system operation is constructed in the form of the sequence of events related to the number of redundant modules. Such an approach results in relatively simple expressions for both reliability and failure rate functions of the system. The appropriate results for a k -out-of- n : G system and its variations such as NMR and NMR/Simplex are derived. The problem of compensating logical faults is also considered.

Fast and accurate thermal modeling and simulation of manycore processors and workloads

Todays microprocessors require careful analysis of their thermal behavior both at design time as well as at runtime. However, accurate prediction of thermal behavior is possible only through simulations due to the complexity and the high dynamicity of their operation. Unfortunately, accurate simulations of such complex systems are computationally intensive, therefore time consuming, while on the other hand, simplified models often cause mispredictions leading to overdesign and lowered performance. In our work, we propose a new discrete-time method of assessment of the run-time temperature of a processor based on an approximation of its instructions-per-cycle (IPC) by a finite Fourier series expansion. Our method is AC-based, and shows significant increase of accuracy in comparison to well-known DC (average)-based models. Furthermore, we provide a new Dynamic Voltage and Frequency Scaling (DVFS) model based on our estimations.

Self-Dual Modules in Design of Dependable Digital Devices

The class of self-dual logic circuits is analyzed. It is shown, that self-duality is the feature of a numerous arithmetic circuits, like elementary 1-bit adder, standard binary and 2s complement adders and a class of modulo adders

Synthesis of Multithreshold Threshold Gates

This paper presents novel synthesis algorithm capable of generating Multithreshold Threshold Gate (MTTG) structure for arbitrary Boolean function. Algorithm draws from dedicated efficient threshold decomposition procedure that represents Boolean function as a min/max composition of threshold functions. Since the proposed threshold decomposition procedure outputs minimal number of thresholds therefore the resulting gate is compact - for k-threshold n-input Boolean function at most (k+1)(n+1) NDR elements in a (k+1)-level gate structure, and (k+1)n transistors are required.

Synthesis of Generalised Threshold Gates and Multi Threshold Threshold Gates

We present formal models and efficient synthesis algorithms for threshold gates of Generalised Threshold Gate (GTG) and Multi Threshold Threshold Gate (MTTG) structures. For GTG synthesis our method does not require to calculate thresholds, that separate function onset and offsets, which greatly simplifies and speeds up the synthesis algorithm. For MTTG we propose a novel synthesis method that determines structure and circuit parameters efficiently. As complexity of MTTG circuit increases with number of thresholds we have developed a dedicated heuristic for efficiently determining the number of required thresholds. The number of resulting thresholds is smaller compared to the number of thresholds calculated using other methods.

Synthesis of logic circuits based on negative differential resistance property

This paper deals with negative differential resistance and its application to construction of threshold gates. We present evaluation of two synthesis algorithms for Generalised Threshold Gates and formulate properties and general steps of synthesis for Multi Threshold Threshold Gates.