Kuan-Ju Huang

A real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination

This paper presents a real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination. Since EEG signals are one of the feeblest physiological electrical signals, it is easily contaminated by artifacts. Previously, ICA was used to extract artifacts from an EEG data segment in a time period. After processing of ICA, automatic artifact detection and elimination are performed. After that, artifact free EEG signals are reconstructed. Recently, many kinds of EEG applications such as BCIs are proposed to control machines through EEG directly. In order to make BCIs more feasible and reliable, the EEG signals used for BCIs need to be acquired from human without artifacts in real-time. In this work, a real-time ICA algorithm, ORICA, is adopted. Since eye blink artifact dose the most significant harm to EEG signals, this work focus on the automatic eye blink artifact elimination and the algorithm used for eye blink artifact detection is sample entropy. With these algorithms and the real-time processing flow we proposed, processing result of each EEG raw data is finished in 0.25 s after each sample time. In the end of this paper, the method used to evaluate the performance of eye blink artifact elimination is provided. Real EEG signals are also processed and the operation results are shown to remove the eye blink artifacts exactly without misses.

An online recursive ICA based real-time multichannel EEG system on chip design with automatic eye blink artifact rejection

This paper presents an online recursive ICA (ORICA) based real-time multi-channel EEG system on chip design with automatic eye blink artifact rejection. Since EEG signals are very feeble, they are easy to be contaminated by artifacts. Among all artifacts, eye blink artifact dose the most significant harm to EEG signals. For acquiring artifact free EEG signals, ICA is a popular method for artifacts extraction. After extraction of ICA, eye blink artifacts are rejected to improve the reliability of EEG applications such as brain computer interfaces (BCIs). To promote the feasibility and convenience of BCIs, a real-time ICA algorithm, ORICA, is adopted in this system. With ORICA, the system immediately finishes each ICA result after each sample time. After each ICA result is generated, the automatic eye blink artifact rejection and inverse ICA are performed to acquire eye blink artifact free EEG signals in realtime. For system portability and high integration, a front-end interface of commercial IC, ADS1298 provided by TI, and Bluetooth interface, UART, are implemented. The system is designed used TSMC 90nm CMOS technology with 8 channels EEG processing in 128 Hz sample rate of raw data and consumes 8.56 mW at 50 MHz clock rate. The design methods of the proposed EEG system are provided in this paper. The performance and processing results of the system are also shown to reach 0.2532 s latency after each EEG sample time.

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um2, and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation

This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1s frame is 0.9763.

An Efficient VLSI Implementation of SVD Processor of On-line Recursive ICA for Real-time EEG System

This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.

A VLSI design of singular value decomposition processor used in real-time ICA computation for multi-channel EEG system

This paper presents a VLSI design of singular value decomposition (SVD) processor used in real-time independent component analysis (ICA) computation for multi-channel electroencephalography (EEG) system. EEG signals are easily influenced by other artifacts. To acquire artifact free EEG signals, ICA is a popular method for artifact removal. Results obtained after the pre-processing of ICA are often used for further applications such as brain computer interfaces (BCIs). In order to improve the feasibility and convenience of BCIs, a real-time ICA pre-processing is required. Because SVD is used frequently in computations of ICA, a SVD processor used for real-time ICA computation is essential. This paper aims to develop a custom SVD for multi-channel EEG systems based on ICA. During the ICA process, the proposed processor aims to solve the inverse and inverse square root matrices in real time. And the processor obtains a highly accurate result since a novel design concept for renewing data flow and parallel data processing are provided in this research. This processor is developed with TSMC 90nm CMOS technology in an 8-channel EEG system. The performance of the proposed SVD is also provided with the processing result of the EEG system.

A parallel VLSI architecture of singular value decomposition processor for real-time multi-channel EEG system

This paper presents a parallel VLSI architecture of a singular value decomposition (SVD) processor for real-time multi-channel electroencephalography (EEG) System. In the recent years, EEG has been widely applied on engineering research, medical diagnosis, and so on. More and more studies regarding brain-computer interface (BCI) and other related applications have been published. In order to increase the accuracy of BCI, the need for a real-time multi-channel EEG System is very urgent. Because an EEG system uses a SVD processor to calculate inverse matrix of target ones, the real-time requirement of the EEG system depends on the operation latency of the SVD processor. Moreover, the accuracy of results obtained from SVD processor directly affects the performance of the system. Generally, SVD is based on coordinate rotation digital computer (CORDIC) algorithm in hardware implementation. Therefore, there is a trade-off between the iteration number of the CORDIC engine, which is related to the computing latency of the SVD processor, and accuracy of SVD the results. In this paper, the parallel architecture of the SVD processor can efficiently shorten the clock cycle of iteration times and provide a precise inverse matrix result. This work not only upgrades the EEG system practicability, but also ensures the feasibility of real-time application. The proposed SVD processor is implemented in the 8-channel EEG system using the TSMC 90 nm CMOS technology.

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.