Kuan-Lin Chen

Using MEMS to Build the Device and the Package

MEMS devices must be packaged to be used. Unfortunately, MEMS packages are challenging to develop, and the packaging of MEMS devices often dominates the cost of the product. In recent years, our group has worked with a team from Bosch to develop and demonstrate a novel wafer-scale encapsulation approach for MEMS. This process uses MEMS fabrication steps to build the device and the package at the same time. The main advantage of this approach is that the wafers emerge from the fabrication facility with all the fragile MEMS structures completely buried within the wafer, allowing all existing standard handling and packaging approaches, such as wafer-dicing, pick/place, and injection mold packaging to be used. This encapsulation process enables CMOS integration, embedding, and extreme miniaturization of complete systems. In this paper, we describe some advantages for performance, size and cost that can come from this approach.

Wafer-Level Epitaxial Silicon Packaging for Out-of-Plane RF MEMS Resonators With Integrated Actuation Electrodes

This paper presents an integrated solution for wafer-level packaging and electrostatic actuation of out-of-plane radio frequency microelectromechanical system resonators. By integrating the electrodes into the epitaxial-grown silicon layer, both the encapsulation and the out-of-plane actuation can be built in one process step, which results in an ultracompact and robust packaging. First, designs and fabrication processes of the out-of-plane electrode are described. The mechanical and electrical properties of the electrode are discussed, modeled, and characterized. A 200 kHz torsional mode beam resonator and an 11.2 MHz transverse-mode differential square plate resonator are fabricated using this packaging method and their performances are presented and discussed.

The long path from MEMS resonators to timing products

Research on MEMS Resonators began over 50 years ago. In just the last 10 years, there has been a series of important technological developments, and (finally!) success at commercialization. The presentation will highlight some key milestones along this path, describe some of the critical technology steps, and outline some of the important non-technological events within SiTime - all of these factors contributed to the successful outcome.

Encapsulated out-of-plane differential square-plate resonator with integrated actuation electrodes

This paper presents a fully encapsulated 12.5 MHz transverse-mode differential square plate resonator that has out-of-plane actuation electrodes integrated into the thinfilm microshell encapsulation. The integration of electrodes minimizes the parasitic resistance, which is generally large for out-of-plane device, and the total footprint of the resonator. Feedthrough capacitance is also minimized by utilizing a differential topology. The AC power handling and DC tuning characteristics are also presented. The plate resonator has no noticeable frequency shift even for AC driving voltages ranging from 223 mV to 2.23 V. The center frequency is still tunable by changing the DC bias voltage, which is ideal for applications that require frequency tunability.

Epitaxial Silicon Microshell Vacuum-Encapsulated CMOS-Compatible 200 MHz Bulk-Mode Resonator

This paper shows the first successful combination of dielectrically-transduced 200 MHz resonators with the epi-silicon encapsulation process, and demonstrates a set of important capabilities needed for the construction of CMOS-compatible RF MEMS components. The result shows the resonant frequency of 207 MHz and a quality factor of 6,400. The high f.Q (1.2×1012 Hz) makes this encapsulated resonator an excellent candidate for applications in local oscillators and RF spectrum analyzers.

Performance Evaluation and Equivalent Model of Silicon Interconnects for Fully-Encapsulated RF MEMS Devices

This paper aims to demonstrate the utility of silicon interconnects for radio-frequency (RF) microelectromechanical system (MEMS) devices that are packaged using a wafer-scale encapsulation process. Design and fabrication steps for the packaged interconnects are described. Measurement results show that encapsulated devices can be operated at frequencies up to 6 GHz with less than 1 dB insertion loss from the through-package silicon interconnects. This paper also describes a simple and accurate lumped-element model for simulating the performance of packaged silicon interconnects. The model is verified with S-parameter measurements from 50 MHz to 6 GHz. The modeling method and extracted values are intended to aid in the design and simulation of RF MEMS devices packaged using this technology.

Wafer Scale Encapsulation of Wide Gaps using oxidation of Sacrificial Beams

This paper explores the possibility of using oxidation of sacrificial beams to encapsulate wide gaps. This method of oxidizing silicon beams in order to create diffusion barriers and structural supports has been reported in literatures. The idea is to encapsulate gaps of various widths in a method that is independent of the width of the gaps. In this experiment we try to encapsulate devices and structures with large gaps of the order of 10-20 mum using this technique and observe the results through SEM images.

Acceleration Compensation of MEMS Resonators using Electrostatic Tuning

A method of using electrostatic tuning to compensate the phase noise due to external vibrations in a MEMS oscillator is presented in this paper. An accelerometer measures the acceleration applied to a resonator, and a compensation signal generated by the accelerometer is added to the bias voltage. We achieve 91% reduction of the acceleration sensitivity for sinusoidal accelerations from 100 Hz to 300 Hz using a double-ended tuning fork resonator. This is the first demonstration of active acceleration compensation for MEMS resonators.

Development of Process for Wafer Scale Encapsulation of Devices With Very Wide Trenches

A Wafer scale encapsulation process has been developed for devices that require wide gaps. In this experiment, we focus on devices that have gaps or trenches 10-20μm wide. This process can also be applied to larger gaps of the order of 50-100μm. The chief focus of the process development is to achieve a wafer scale encapsulation technique, which can avoid deposition of very thick LPVCD oxide. Once the processing and encapsulation is carried out, SEM images are taken to ensure that the device is completely released and no sacrificial material is left behind.Copyright