Kumar Yelamarthi

RFID and GPS integrated navigation system for the visually impaired

This paper describes an RFID and GPS integrated navigation system, Smart-Robot (SR) for the visually impaired. The SR uses RFID and GPS based localization while operating indoor and outdoor respectively. The portable terminal unit is an embedded system equipped with an RFID reader, GPS, and analog compass as input devices to obtain location and orientation. The SR can guide the user to a predefined destination, or create a new route on-the-fly for later use. While in navigation mode, the SR reaches the destination by avoiding obstacles using ultrasonic and infrared sensor inputs. The SR also provides user feedback through a speaker, and vibrating motors on the glove. The SR prototype has been successfully implemented and is operational.

RFID positioning robot: An indoor navigation system

This paper describes a system to improve indoor navigation through use of radio frequency identification (RFID) technology. The terminal unit is an embedded system equipped with an RFID reader for localization, a mobile robot for navigation, and a combination of ultrasonic and IR sensors for obstacle detection and avoidance during navigation. To increase accuracy of an indoor guidance system, a triangulation method is proposed to accurately detect the location. While the proposed method can be verified by many methods, the accuracy is demonstrated through use of a mobile robot. It navigates to a designated location through continuously monitoring all RFID tags in the vicinity, localizing itself, and calculating the path to the destination.

An RFID based autonomous indoor tour guide robot

This paper describes a radio frequency identification (RFID) and sonar-guided tour guide robot, CATE (Centrals Automated Tour Experience). The portable terminal unit is an embedded system equipped with an RFID reader for localization, and sonar and IR sensors for obstacle detection and avoidance. CATE can guide the visitor through a predefined tour of the building, or create a new route on-the-fly. While in predefined tour mode, CATE completes the tour by avoiding obstacles using sonar and infrared sensor input. It will also provide audio and video information through an onboard computer, and can collect feedback from the user through a touch screen display. CATE has been successfully implemented and is under final stages of testing.

Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.

Internet of Things (IoT) Platform for Structure Health Monitoring

Increase in the demand for reliable structural health information led to the development of Structural Health Monitoring (SHM). Prediction of upcoming accidents and estimation of useful life span of a structure are facilitated through SHM. While data sensing is the core of any SHM, tracking the data anytime anywhere is a prevailing challenge. With the advancement in information technology, the concept of Internet of Things (IoT) has made it possible to integrate SHM with Internet to track data anytime anywhere. In this paper, a SHM platform embedded with IoT is proposed to detect the size and location of damage in structures. The proposed platform consists of a Wi-Fi module, a Raspberry Pi, an Analog to Digital Converter (ADC), a Digital to Analog Converter (DAC), a buffer, and piezoelectric (PZT) sensors. The piezoelectric sensors are mounted as a pair in the structure. Data collected from the piezoelectric sensors will be used to detect the size and location of damage using a proposed mathematical model. Implemented on a Raspberry Pi, the proposed mathematical model will estimate the size and location of structural damage, if any, and upload the data to Internet. This data will be stored and can be checked remotely from any mobile device. The system has been validated using a real test bed in the lab.

An Application-Driven Modular IoT Architecture

Building upon the advancements in the recent years, a new paradigm in technology has emerged in Internet of Things (IoT). IoT has allowed for communication with the surrounding environment through a multitude of sensors and actuators, yet operating on limited energy. Several researchers have presented IoT architectures for respective applications, often challenged by requiring major updates for adoption to a different application. Further, this comes with several uncertainties such as type of computational device required at the edge, mode of wireless connectivity required, methods to obtain power efficiency, and not ensuring rapid deployment. This paper starts with providing a horizontal overview of each layer in IoT architecture and options for different applications. Then it presents a broad application-driven modular architecture, which can be easily customized for rapid deployment. This paper presents the diverse hardware used in several IoT layers such as sensors, embedded processors, wireless transceivers, internet gateway, and application management cloud server. Later, this paper presents implementation results for diverse applications including healthcare, structural health monitoring, agriculture, and indoor tour guide systems. It is hoped that this research will assist the potential user to easily choose IoT hardware and software as it pertains to their respective needs.

Target localization in Wireless Sensor Network based on Time Difference of Arrival

One of the most prominent challenges in Wireless Sensor Network (WSN) is target localization. As majority of the decisions made in navigation and path planning are dependent on current information available, target localization is one of the fundamental requirements. This paper presents accuracy studies on target localization using the Time Difference of Arrival (TDOA) method. An evaluation of the TDOA is presented through a random reference node by using four stationary sensors in a sensor network. Some of the fundamental advantages in the presented method are its simplicity through requiring only four reference nodes, tolerating errors in node positioning and time differences. Simulations results show that proposed TDOA method outperforms the centroid TDOA method in different test environments, with an average localization error of 2.36 m.

Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay was optimized from 355 to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also optimized, of which the critical path delay was reduced from 152 to 103 ps which accounts for a 32.23% delay improvement, and delay uncertainty was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay and the power-delay-product were optimized to 632 ps and 84.17 pJ, respectively.

Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

The complexity in timing optimization of high performance microprocessors has been increasing with the number of channel-connected transistors in various paths of dynamic CMOS circuits and the rising magnitude of process variations in nanometer CMOS process. In this paper, a process variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load Balance of Multiple Paths (LBMP) is proposed. The proposed iterative optimization algorithm is a deterministic approach and is illustrated first by a 2-b weighted binary-to-thermometric converter (WBTC) and of which the critical path was optimized from an initial delay of 355 ps to an optimal delay of 157 ps, which accounts for a 55.77% delay improvement. A 4-b unity weight binary-to-thermometric converter (UWBTC) was also designed and of which the critical path was optimized from an initial delay of 152 ps to an optimal delay of 103 ps, which accounts for a 32.23% delay improvement. Finally, a 64-b parallel binary adder was partitioned to a mixed dynamic-static CMOS style and the critical path and the power delay product were optimized to 632 ps and 84.17 pJ respectively.