Kumardeb Banerjee

A novel FPGA-based LVDT signal conditioner

This paper presents a phase compensated novel signal conditioner for a linear variable differential transformer (LVDT) and its FPGA based implementation. The LVDT output signal is a double-sideband suppressed-carrier amplitude-modulated (DSB-SC-AM) waveform, where the LVDT sinusoidal excitation is the carrier signal and the LVDT core position is the modulating signal. The proposed signal conditioner locates the carrier peaks in the LVDT output signal and provides a direct digital demodulation of the same at the said instants. Since the carrier component at the sampling instants equals the carrier amplitude, a simple gain scaling converts the read data to the LVDT core position measurement. The peak sensitive demodulation is insensitive to sensor induced phase lag and does not require external phase compensation network. This conditioner has better dynamic response than existing LVDT signal conditioners. Its overall error figures are also comparable with those of the existing solutions.

Fast prototyping of a digital PID controller on a FPGA based soft-core microcontroller for precision control of a brushed DC servo motor

Design and analysis of Digital Proportional Integral Derivative (PID) controllers for digital motion control involving dc motors are well documented and commercial/industrial off-the-shelf solutions are readily available. Majority of the said controllers are designed to work with brushless dc motors. However, many existing two-axis and three-axis gimbaled systems work with conventional analog PID controllers, brushed dc motors and synchros as position sensors. Whenever there is a need for a replacement of the electronics of similar systems, the analog electronics is replaced by digital equivalent. The choice of using off-the-shelf solutions is rather limited because of the prime mover and the output sensing devices. Design and implementation of a case-specific processor based solution is often the only cost-effective option. The present work proposes the step-by-step procedure for the fast prototyping of a digital PID controller for brushed dc motors on an FPGA-based SoftCore Microcontroller. The input section consists of an analog signal conditioner for scaling the reference input and the sensed feedback signal, a serial analog-to-digital converter (SADC) and a programmable gain amplifier (PGA). The output stage consists of an H-bridge power amplifier for driving the armature circuit of the dc servo motor (DCSM). The platform used is a Spartan 3E FPGA (x3s500E) with an embedded 8-bit PicoBlaze microcontroller. Though a single-axis implementation is documented, it can easily be extended for two-axis and three-axis systems using multiple soft-core processors embedded on the same FPGA.

An in situ trap capacitance measurement and ion-trapping detection scheme for a Penning ion trap facility

This paper presents the design and implementation of an in situ measurement setup for the capacitance of a five electrode Penning ion trap (PIT) facility at room temperature. For implementing a high Q resonant circuit for the detection of trapped electrons/ions in a PIT, the value of the capacitance of the trap assembly is of prime importance. A tunable Colpitts oscillator followed by a unity gain buffer and a low pass filter is designed and successfully implemented for a two-fold purpose: in situ measurement of the trap capacitance when the electric and magnetic fields are turned off and also providing RF power at the desired frequency to the PIT for exciting the trapped ions and subsequent detection. The setup is tested for the in situ measurement of trap capacitance at room temperature and the results are found to comply with those obtained from measurements using a high Q parallel resonant circuit setup driven by a standard RF signal generator. The Colpitts oscillator is also tested successfully for supplying RF power to the high Q resonant circuit, which is required for the detection of trapped electrons/ions.

An FPGA-based integrated signal conditioner for measurement of position, velocity and acceleration of a rotating shaft using an incremental encoder

Digital motion control applications, where electric motors are utilized as actuators, use incremental encoders as feedback devices to sense the rotating shaft position. However, for the controller to implement an accurate tracking of input position or velocity trajectories, and to make the tracking performance robust with respect to unpredictable disturbances like parameter uncertainties and load fluctuations, measurement of velocity and acceleration data is also required. In majority of the existing digital motion control solutions, direct measurement of velocity and acceleration is rarely done. Instead, they are estimated from the discrete position data obtained from the incremental encoder. Well documented velocity and acceleration estimation algorithms exist, and the literature report both simulation and experimental results on the performance of the said algorithms with typical input position trajectories. However, no integral hardware module that uses an incremental encoder to provide position, velocity and acceleration measurement is reported. This paper presents the design and FPGA-based implementation of an integrated signal conditioner that uses the signals coming from an incremental encoder to measure the current position, and then estimate the current velocity and acceleration from it, and its performance on a test-rig. With a fast, industry-standard serial link, the proposed signal conditioner qualifies to be an integrated feedback device in digital motion control applications.

A carrier peak synchronous direct digital demodulation technique and its FPGA implementation

Abstract This paper presents a carrier peak synchronous direct digital demodulation scheme for linear modulated signals and its innovative FPGA implementation. The demodulation scheme generates a carrier equivalent signal that is in quadrature with the modulated signal and strobes the modulated signal at the carrier peaks. A digitizer in the form of an analog to digital converter now converts the sampled data to a digital count, thereby producing a direct digital read-out of the modulated signal. This obviously eliminates the necessity of the standard sequence of multiplication, low pass filtering and subsequent processing common in existing analog and digital synchronous quadrature demodulators. Removal of the low pass filtering stage eliminates the inherent filter time lag that proves beneficial in those measurement applications where exact phase sensitive detection of the measurand at specific time instant is important. The feasibility of the proposed scheme is established through its FPGA implementation for reconstructing the modulating signal by sampling the modulated signal at every carrier peak and holding the sampled value till the next sampling instant. The implementation is found to automatically capture and remain tuned to any carrier frequency in the range 763 Hz to 100 kHz.

Development of low noise amplifier and associated RF switching circuit for the penning ion trap

In this paper we describe the design and development of cryogenic electronic instrumentation required for VECC cryogenic Penning ion trap facility. As a part of the development of cryogenic electronic instrumentation, a low noise amplifier based on GaAs technology is designed and room temperature testing of the amplifier is successfully accomplished. The equivalent input voltage noise density of the amplifier measured at room temperature is found to be in the range of (1.8.2)nV Hz at the ion trap axial frequency of 63 MHz. Also a cryogenic switching and RC filtering circuit is developed in order to maintain proper switching of RF energy used to excite the motional amplitude of trapped electrons. These RC filtering circuits filter the noise in the DC supply lines. The performance of this circuit board has been tested successfully upto 90K.

System identification for unmanned marine vehicles using interval analysis

The aim in the present paper remains to describe a system identification method for unmanned marine vehicles using interval analysis in order to come up with estimation of parameter intervals instead of real values, such that the actual dynamics of the system shall remain confined within guaranteed bounds. The bounds are propagated through the system equations using such interval based parameters. The proposed method exploits guaranteed error bounds for the state variables as observed by different sensors. Unlike conventional Kalman estimators the adopted method rules out the requirement for determining co-variance matrices and approximated Jacobians. Interval based variables are used in constructing interval matrices. Principle of Least Squares is used in solving the system equation involving such non-punctual (interval) matrices. In this context a sophisticated interval matrix inversion technique is employed within the least squares framework in finally determining the parameter intervals.

GPU accelerated novel particle filtering method

In this paper, a graphics processor unit (GPU) accelerated particle filtering algorithm is presented with an introduction to a novel resampling technique. The aim remains in the mitigation of particle impoverishment as well as computational burden, problems which are commonly associated with classical (systematic) resampled particle filtering. The proposed algorithm employs a priori-space dependent distribution in addition to the likelihood, and hence is christened as dual distribution dependent (D3) resampling method. Simulation results exhibit lesser values for root mean square error (RMSE) in comparison to that for systematic resampling. D3 resampling is shown to improve particle diversity after each iteration, thereby affecting the overall quality of estimation. However, computational burden is significantly increased owing to few excessive computations within the newly formulated resampling framework. With a view to obtaining parallel speedup we introduce a CUDA version of the proposed method for necessary acceleration by GPU. The GPU programming model is detailed in the context of this paper. Implementation issues are discussed along with illustration of empirical computational efficiency, as obtained by executing the CUDA code on Quadro 2000 GPU. The GPU enabled code has a speedup of 3 and 4 over the sequential executions of systematic and D3 resampling methods respectively. Performance both in terms of RMSE and running time have been elaborated with respect to different selections for threads per block towards effective implementations. It is in this context that, we further introduce a cost to performance metric (CPM) for assessing the algorithmic efficiency of the estimator, involving both quality of estimation and running time as comparative factors, transformed into a unified parameter for assessment. CPM values for estimators obtained from all such different choices for threads per block have been determined and a final value for the chosen parameter is resolved for generation of a holistic effective estimator.