Kun-Mo Chu

Compact packaging of optical and electronic components for on-board optical interconnects

An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45/spl deg/ mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links.

Origin of the discrepancy between photoluminescence brightness of TAG:Ce and electroluminescence brightness of TAG:Ce-based white LED expected from phosphor brightness.

A yellow-emitting Tb(3)Al(5)O(12):Ce(3+) (TAG:Ce) phosphor was coated on blue light-emitting diodes (LEDs) to obtain white LEDs (WLEDs). Since TAG:Ce showed 90% of the brightness of Y(3)Al(5)O(12):Ce(3+) (YAG:Ce), it was expected that TAG:Ce-based WLEDs showed 90% of brightness of YAG:Ce-based ones. However, the TAG:Ce-based WLED showed 74% of the brightness of YAG:Ce-based one. Considering the density and size of the phosphors, the higher density and larger size of TAG:Ce induced a great deal of sedimentation of TAG:Ce particles in an epoxy resin. It is believed that this is one of main reasons for the reduced optical power of the TAG:Ce-based WLED compared to that of the WLED expected from the brightness of TAG:Ce.

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7degC. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps

Flip-Chip Bonding of MEMS Scanner for Laser Display Using Electroplated AuSn Solder Bump

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages

Characteristics of Indium Bump for Flip-Chip Bonding Used in Polymeric-Waveguide-Integrated Optical Interconnection Systems

We have flip-chip-bonded vertical-cavity surface-emitting laser (VCSEL) arrays on polymeric-waveguide-integrated optical interconnection systems. Using indium solder bumps, thermal damage to the polymeric waveguide can be avoided. Fracture occurs between the indium solder bumps and the VCSEL chip pad during the die shear test. It is inferred that both the low bonding temperature and the oxide layer formed on the surface of the indium solder prevent the bump from interacting with the chip pad. To reveal the microstructures of the joints between the bump and the chip pad, several specimens are cut into cross sections and polished. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system is used to examine the microstructures and analyze the element compositions. Also, the optoelectronic characteristics of VCSEL arrays that were flip-chip-bonded under different bonding conditions are compared by current-voltage (I-V) and light-current (L-I) inspection.

A fluxless flip chip bonding for VCSEL arrays using silver coated indium solder bumps

Alloys of lead-tin system are the most common solder alloys used today. However, there are environmental and health issues concerning the toxicity of lead present in these lead-tin solder alloys. Also, the flux residue removal is mandatory and leads to environmental threats. More importantly, the use of flux may contaminate the optically active surface by organic residue leftover, and a conventional cleaning method may not be effective for optoelectronic assemblies. Therefore, it is necessary to look for fluxless soldering processes for soldering optoelectronic systems. In the present study, we have conducted low-temperature flip-chip bonding of vertical-cavity surface-emitting laser (VCSEL) arrays on a glass substrate that provides propagation paths of laser beams and also supports a polymeric waveguide. Considering both the die shear test and the spreading test, the appropriate bonding temperature and pressure using indium solder bump were found to be about 150/spl deg/C/500 gf. The fracture occured between the indium solder bump and the VCSEL chip pad during the die shear test. It is inferred that both the low bonding temperature and the oxide layer which is formed on the surface of the indium solder prevented the bump from interacting with the chip pad. We expect the thin silver layer coating on the indium bump to protect the inner indium solder from oxidation and to decrease the melting temperature of the indium solder. Thus, we try coating a thin silver layer onto the indium surface. An eutectic reaction occurs at 97 wt.% of In with an eutectic point of 144/spl deg/C and the outer silver layer interacts with indium to form a AgIn/sub 2/ compound layer due to the high interdiffusion coefficient. As a result, the thin silver layer coated on the solder bump is very effective to enhance the adhesion strength between the indium bump and the VCSEL chip pads by decreasing the melting temperature of the indium solder bump locally.

Formation and characterization of cobalt-reinforced Sn-3.5Ag solder

Solders under severe service environments should have enhanced mechanical properties. To achieve this goal, the approach of composite solder reinforced by second-phase particles was tried in this study. Cobalt (Co) and eutectic Sn-3.5Ag were selected as a reinforcing particle and solder matrix, respectively. Co particles and solder paste were mechanically mixed to make uniform mixing at Co weight fractions from 0.1 % to 2.0 %. For the Co-mixed Sn-3.5Ag solder pastes, melting temperature and spreading area were measured. The solder pastes were stencil printed on test substrates and reflowed to form solder bumps. Ball shear test was performed to examine shear strength of Co-reinforced Sn-3.5Ag solder bumps. As a result, small amount of Co addition did not alter melting temperature and spreadability. Maximum shear strength of Co-reinforced Sn-3.5Ag solder bumps showed 28 % increase compared to normal ones. The increase in shear strength was due to facetted needle-like (Cu,Co)3Sn2 intermetallic compounds (IMCs)

Shear strength of Sn-3.5Ag solder bumps formed on Ni/Au and organic solderability preservative surface-finished bond pads after multiple reflow steps

Sn–3.5Ag solder bumps were formed on electroless Ni/immersion Au (Ni/Au) and organic solderability preservative (OSP) surface-finished bond pads, respectively. The shear strength of the solder bumps was measured as a function of reflow steps. Fracture surfaces and interfacial microstructures were investigated by scanning electron microscope. The shear strength of Ni/Au samples increased up to the seventh reflow step and subsequently decreased after the tenth reflow step. Spalling of Ni3Sn4 intermetallic compounds (IMCs) and the P-rich Ni layer strengthened and weakened the bond, respectively. For OSP samples, although Cu6Sn5 IMCs grew as the reflow step was repeated, no remarkable change in shear strength was observed. Interfacial fractures of OSP samples occurred at the interface between Cu6Sn5 IMC and Cu3Sn IMC. Fracture surfaces of OSP samples showed concave pits that consisted o faC u 3Sn bottom and an Sn wall. The pits were formed by separation of Cu6Sn5 IMC from Cu3Sn IMC and the molten Sn channel between the Cu6Sn5 IMC grains.

Formation of fine pitch solder bumps on polytetrafluoroethylene printed circuit board using dry film photoresist

We demonstrated the applicability of dry film photoresists (DFR) in photolithography process for fine pitch bumping on the polytetrafluoroethylene (PTFE/Teflon/spl reg/) printed circuit board (PCB). The copper lines were formed with 100/spl mu/m width and 18/spl mu/m thickness on the PTFE test board, and varying the gaps between two copper lines in a range of 100-200/spl mu/m. The DFRs of 15/spl mu/m thickness were laminated by hot roll laminator, by varying laminating temperature from 100/spl deg/C to 150/spl deg/C and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of 150/spl deg/C and speed of about 0.63cm/s. And the smallest size of indium solder bump was diameter of 50/spl mu/m with pitch of 100/spl mu/m.