Kunal Banerjee

Verification of Code Motion Techniques Using Value Propagation

An equivalence checking method of finite state machines with datapath based on value propagation over model paths is presented here for validation of code motion transformations commonly applied during the scheduling phase of high-level synthesis. Unlike many other reported techniques, the method is able to handle code motions across loop bodies. It consists in propagating the variable values over a path to the subsequent paths on discovery of mismatch in the values for some live variable, until the values match or the final path segments are accounted for without finding a match. Checking loop invariance of the values being propagated beyond the loops has been identified to play an important role. Along with uniform and nonuniform code motions, the method is capable of handling control structure modifications as well. The complexity analysis depicts identical worst case performance as that of a related earlier method of path extension which fails to handle code motion across loops. The method has been implemented and satisfactorily tested on the outputs of a basic block-based scheduler, a path-based scheduler, and the high-level synthesis tool SPARK for some benchmark examples.

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors

Loop transformation techniques along with arithmetic transformations are applied extensively on array and loop intensive behaviors in design of area/energy efficient systems in the domain of multimedia and signal processing applications. Ensuring correctness of such transformations is crucial for the reliability of the designed systems. In this paper, array data dependence graphs (ADDGs) are used to represent both the input and the transformed behaviors and the correctness of the transformations is ensured by proving equivalence of the two ADDGs. A slice-based equivalence checking method of ADDGs is proposed for this purpose. The method relies on the normalization of arithmetic expressions and some simplification rules to handle arithmetic transformations. Unlike many other reported techniques, our method is strong enough to handle several arithmetic transformations along with all kinds of loop transformations. Correctness and complexity of the method have been dealt with. Experimental results on several test cases demonstrate the effectiveness of the method.

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques

A novel value propagation based equivalence checking method of finite state machines with datapath (FSMDs) is presented here for validation of code motion transformations commonly applied during scheduling phase of high-level synthesis. Unlike many other reported techniques, our method is able to handle code motions across loop bodies. This is accomplished by repeated propagation of the mismatched values to subsequent paths until the values match or the final path segments are traversed without finding a match. Checking loop invariance of the values being propagated beyond the loops has been underlined to play an important role. The proposed method is capable of handling control structure modification as well. The method has been implemented and satisfactorily tested for some benchmark examples.

Equivalence Checking of Array-Intensive Programs

An equivalence checking method for ensuring correctness of loop and arithmetic transformations in array intensive programs is presented here. The array data dependence graphs (ADDGs) are used to represent both the input and the transformed behaviours and the correctness of the transformations is ensured by proving equivalence of two ADDGs. In contrast to the existing path based one, we formalize a slice based equivalence of ADDGs. Moreover, normalization of arithmetic expressions and some simplification rules are incorporated to handle arithmetic transformations. Experimental results on several test cases demonstrate the effectiveness of our method.

Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs

The finite state machine with datapath (FSMD) models provide a formalism to represent any sequential behavior. Literature has many examples where this model has been successfully applied for behavioral verification of programs. All these methods, however, cannot handle an important class of programs, namely those involving arrays. This limitation is now overcome with finite state machine with datapath having arrays (FSMDA) models which are an extension of FSMD models; the corresponding equivalence checking algorithm has also been enhanced so that code motions of array-intensive behaviors can be validated. The new mechanism has been successfully tested with several examples.

Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker

Behavioural equivalence checking of the refinements of the input behaviours taking place at various phases of synthesis of embedded systems or VLSI circuits is a well pursued field. Although extensive literature on equivalence checking of sequential behaviours exists, similar treatments for parallel behaviours are rare mainly because of all the possible execution scenarios inherent in them. Here, we propose a translation algorithm from a parallel behaviour, represented by an untimed PRES+ model, to a sequential behaviour, represented by an FSMD model. Several equivalence checkers for FSMD models already exist for various code based transformation techniques. We have satisfactorily performed equivalence checking of some high level synthesis benchmarks represented by untimed PRES+ models by first translating them into FSMD models using our algorithm and subsequently feeding them to one such FSMD equivalence checker.

A path-based equivalence checking method for Petri net based models of programs

Programs are often subjected to significant optimizing and parallelizing transformations. It is therefore important to model parallel behaviours and formally verify the equivalence of their functionalities. In this work, the untimed PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours. Being value based with inherent scope of capturing parallelism, PRES+ models depict such data dependencies more directly; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both the source and the transformed codes for translation validation than strictly sequential variable-based IRs like Finite State Machines with Datapath (FSMDs) (which are essentially sequential control data-flow graphs (CDFGs)). In this work, a path based equivalence checking method for PRES+ models is presented.

A Scheme for Automated Evaluation of Programming Assignments using FSMD based Equivalence Checking

This work presents an automated program evaluation scheme by leveraging the equivalence checking method of Finite State Machines with Data-path (FSMDs) which has found extensive application in translation validation of programs. In order to assess a students program, it is compared with a model program supplied by the instructor. Besides reporting the error and providing feedback towards error correction, our method performs automated evaluation of programs which is particularly helpful in an environment where there is a large number of students, thus saving a lot of time for the instructor. Being automated, our scheme will ensure consistency in evaluation and ensure speedy evaluation.

A Path Construction Algorithm for Translation Validation Using PRES+ Models

Multi-core and multi-processor architectures have predominated the domain of embedded systems permitting easy mapping of concurrent applications to such architectures. The programs, in general, are subjected to significant optimizing and parallelizing transformations, automated and also human guided, before being mapped to an architecture. Modelling parallel behaviour and formally verifying that their functionality is preserved during synthesis are challenging tasks. Untimed PRES+ models are found to be suitable for the specification of parallel behaviour. Path cover oriented equivalence checking methods have been found to be quite effective for sequential behaviour. Path construction for parallel behaviour, however, is significantly more complex than that for sequential behaviour due to all possible interleavings of the parallel operations. Identification of the path covers depends upon choosing appropriate cut-points. In this paper, the need for introducing cut-points dynamically has been underlined and a mechanism to achieve this task is proposed. Details on how to construct a path cover using dynamic cut-points is presented.

Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic

Differential power analysis (DPA) attacks are the most powerful side channel attacks against cryptographic systems. In this work, a reduced ordered binary decision diagram (ROBDD) based dual rail circuit for a basic DPA resistant cell has been designed. The specialty of this cell is that the overall input current of the cell is invariant to the input combinations of data bits applied to the cell. For the first time, bottom pre-charge logic is used in the design of such a cell. The ROBDD based design minimizes both area and early propagation effect. A number of logic functions including AND, OR, XOR, NOT, NAND, NOR and also an adder, all based on the basic cell, have then been designed in a hierarchical manner. Experimental results demonstrate DPA resistance of the circuits (for example an adder) developed using this cell, outperforming other competing design with respect to peak power variance.