Soumyadip Bandyopadhyay

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs

The initial behavioural specification of any software programs goes through significant optimizing and parallelizing transformations, automated and also human guided, before being mapped to an architecture. Establishing validity of these transformations is crucial to ensure that they preserve the original behaviour. PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours. Being value based with inherent scope of capturing parallelism, PRES+ models depict such data dependencies more directly; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both the source and the transformed codes for translation validation than strictly sequential variable-based IRs like Finite State Machines with Data path (FSMDs) (which are essentially sequential control flow graphs (CFGs)). In this work, a path based equivalence checking method for PRES+ models is presented.

Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker

Behavioural equivalence checking of the refinements of the input behaviours taking place at various phases of synthesis of embedded systems or VLSI circuits is a well pursued field. Although extensive literature on equivalence checking of sequential behaviours exists, similar treatments for parallel behaviours are rare mainly because of all the possible execution scenarios inherent in them. Here, we propose a translation algorithm from a parallel behaviour, represented by an untimed PRES+ model, to a sequential behaviour, represented by an FSMD model. Several equivalence checkers for FSMD models already exist for various code based transformation techniques. We have satisfactorily performed equivalence checking of some high level synthesis benchmarks represented by untimed PRES+ models by first translating them into FSMD models using our algorithm and subsequently feeding them to one such FSMD equivalence checker.

A path-based equivalence checking method for Petri net based models of programs

Programs are often subjected to significant optimizing and parallelizing transformations. It is therefore important to model parallel behaviours and formally verify the equivalence of their functionalities. In this work, the untimed PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours. Being value based with inherent scope of capturing parallelism, PRES+ models depict such data dependencies more directly; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both the source and the transformed codes for translation validation than strictly sequential variable-based IRs like Finite State Machines with Datapath (FSMDs) (which are essentially sequential control data-flow graphs (CDFGs)). In this work, a path based equivalence checking method for PRES+ models is presented.

An efficient path based equivalence checking for Petri net based models of programs

A user written program goes through significant optimizing and parallelizing transformations, both (compiler) automated and human guided, before being mapped to an architecture. Formally verifying these transformations is crucial to ensure that they preserve the original behavioural specification. The PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours more succinctly. Being value based with a natural capability of capturing parallelism, PRES+ models depict such data dependencies more vividly; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both source and transformed codes for translation validation than strictly sequential, variable-based IRs such as Finite State Machines with Data path (FSMDs) which are essentially sequential control and data flow graphs (CDFGs). This paper presents a scheme for verifying equivalence between two given PRES+ models for translation validation of optimizing and parallelizing code transformations; one of the two models represents the source code and the other represents its optimized and (or) parallelized version.

A Path Construction Algorithm for Translation Validation Using PRES+ Models

Multi-core and multi-processor architectures have predominated the domain of embedded systems permitting easy mapping of concurrent applications to such architectures. The programs, in general, are subjected to significant optimizing and parallelizing transformations, automated and also human guided, before being mapped to an architecture. Modelling parallel behaviour and formally verifying that their functionality is preserved during synthesis are challenging tasks. Untimed PRES+ models are found to be suitable for the specification of parallel behaviour. Path cover oriented equivalence checking methods have been found to be quite effective for sequential behaviour. Path construction for parallel behaviour, however, is significantly more complex than that for sequential behaviour due to all possible interleavings of the parallel operations. Identification of the path covers depends upon choosing appropriate cut-points. In this paper, the need for introducing cut-points dynamically has been underlined and a mechanism to achieve this task is proposed. Details on how to construct a path cover using dynamic cut-points is presented.

Validating SPARK: High Level Synthesis Compiler

Embedded systems have found applications in diverse domains. Due to the criticality of their operations, verification of embedded systems is a necessity. With the advancement of multi-core and multiprocessor systems, there has been a paradigm shift to incorporate these features in embedded systems as well. The initial behavioural specification of a system goes through significant optimizing transformations using automated high level synthesis (HLS) compiler like SPARK, before being mapped to an architecture. Establishing the validity of these transformations is crucial to ensure that correct optimizations are applied during synthesis. To model parallel behaviours, especially in embedded systems, the use of PRES+ models is advocated for. In this paper, two path based equivalence checking methods foruntimed PRES+ models are given. The experimental results demonstrate the efficiency the of the method.

SamaTulyata: An Efficient Path Based Equivalence Checking Tool

An application program can go through significant optimizing and parallelizing transformations, both automated and human guided, before being mapped to an architecture. Formal verification of these transformations is crucial to ensure that they preserve the original behavioural specification. PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours more vividly. This paper presents a translation validation tool for verifying optimizing and parallelizing code transformations by checking equivalence between two PRES+ models, one representing the source code and the other representing its optimized and (or) parallelized version.

PRESGen: A Fully Automatic Equivalence Checker for Validating Optimizing and Parallelizing Transformations

Petri net has been a popular choice of model of computation (MoC) for representing parallel programs. PRES+ is an extension of the traditional Petri net model which is specially equipped to precisely model embedded systems. Since multi-core and multiprocessor systems have proliferated in the domain of embedded systems as well, it has become critical to validate the optimizing and parallelizing transformations which embedded system specifications go through before being implemented in the hardware. PRES+ model based equivalence checkers for validating such transformations already exist. However, construction of the PRES+ models from the original and the translated codes in these equivalence checkers was not done in an automated manner; thus, leaving scope for inaccurate representation of the PRES+ models since they had to be done manually. Moreover, PRES+ model tends to grow more rapidly with the program size when compared to other MoCs, such as FSMD. To tackle these problems, we propose a method for automated construction of PRES+ models from high-level language programs and using an existing translation scheme to convert PRES+ models to FSMD models, we validate the transformations using a state-of-the-art FSMD equivalence checker. Thus, we have effectively composed an end-to-end fully automatic equivalence checker for validating optimizing and parallelizing transformations. The experimental results demonstrate the practical applicability of our method.

Implementing an Efficient Path Based Equivalence Checker for Parallel Programs

User written programs, when transformed by optimizing and parallelizing compilers, can be incorrect, if the compiler is not trusted. So, establishing the validity of these transformations is a crucial and challenging task. For program verification, the PRES+ (Petri net Representation of Embedded Systems) is now well accepted as a model to capture the data and control flow of a program. In this paper, an efficient path based equivalence checking method using a simple PRES+ model (which is easier to generate from a program) for validating several optimizing and parallelizing transformations is proposed. The experimental results demonstrate the efficiency of the method.

Equivalence checking of Petri net models of programs using static and dynamic cut-points

Extensive optimizing and parallelizing transformations are carried out on programs, both by (untrusted) compilers and human experts, before deploying them on some platform architecture which is by and large parallel. It is therefore important to devise some suitable modelling paradigm which is capable of capturing parallelism in such a way that proving equivalence of the source programs and their transformed versions becomes easier. In the present work, an untimed Petri net model with data constraints, called CPN model (Coloured Petri net), is used to model the parallel behaviours. Being value based, such models depict more vividly the data dependencies which lie at the core of such transformations; accordingly, they are likely to provide more suitable internal representations (IRs) of both the source and the transformed programs than the IRs like sequential control flow graphs (CFGs). A path based equivalence checking method for CPN models with rigorous treatment of the complexity and correctness issues have been presented. Experimental results show the effectiveness of the approach.