Kunihiko Ikuzaki

A CMOS 12K gate array with flexible 10Kb memory

A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.

VLSI reliability challenges: from device physics to wafer scale systems

The philosophical and practical differences between Japanese and US IC industries in regard to VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing, are discussed. It is suggested that a new approach to VLSI reliability is needed in response to the paradigm shift being brought about by simple scaling limitations, increased process complexity and application of VLSI to advanced systems. An example of this shift is the movement from simple failure analysis by sampling the output of a manufacturing line to the building-in-reliability approach. To introduce and expand on the building-in reliability approach in VLSIs, the authors discuss the required deeper physical understanding of such important processes as hot-carrier effects, dielectrics and metallization. >

VLSI reliability challenges: From device physics to wafer scale systems

Abstract The philosophical and practical differences between Japanese and American IC industries concerning VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing are discussed. A new challenging approach to VLSI reliability is now greatly needed in response to the “paradigm shift” now being brought about by simple scaling limitations, increased process complexity, and VLSI application to advanced systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the “building-in-reliability” approach. To pursue this technique, greater importance will be attached to a deeper physical understanding (including frequent use of Computer Aided Design, CAD/ Design Automation, DA) of the significant relationships between the input variables and product reliability, and to total concurrent engineering from research labs to production sites. In addition, distributive quality control management being carried out particularly in Japan, where quality improvement is the common concern for every employeee, may be a key factor in overcoming the more difficult reliability problems in the coming giga-scale ICs. Furthermore, fast new VLSI testing methods and new yield-enhancing redundancy techniques, resulting in cost reduction, will be increasingly needed to achieve high reliability for VLSIs with 109 devices on a single chip.

A 130K-gate mainframe chip set

This presentation will cover a mainframe chip set using three VLSIs containing 542K transistors, employing a rapid turn-around standard cell design methodology. Employing 1.3μm buld processing and controlled by an 8-phase clocking system, the chip operates with a cycle time of less than 60ns and an average propagation delay of less than 0.9ns.

A 6,000-gate CMOS gate array

This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.

A 1024-channel multifunction digital switching IC

A 16.3MHz switching IC Implemented in a 1.3μm CMOS technology will be detailed. Functions include bit phase and frame synchronization, 8/16b interface and maintenance tasks. An on-chip 216K RAM with 15ns access time has been implemented. The 8.5mm square chip dissipates 370mW.