Hisao Katto

Hot carrier degradation modes and optimization of LDD MOSFETs

The hot carrier instability and the related device characteristics of Leff= 1µm MOSFETs with Lightly Doped Drain (LDD) structure is evaluated in detail. For the n- dose below 1E13/cm2, a new type of IBB and IG increase was found when the gate bias, VG, was increased toward and over the drain bias, VD, and related new modes of hot carrier instability were confirmed. The instability for the lower VG stress is attributed to the charge build-up at the n- drain region, while the instability for the larger VG stress is attributed to the oxide degradation at both source and drain regions. The device characteristics and the mechanism of instability for n→= 1E13/cm2 are similar to those of conventional devices. It is shown that the instability inherent to the LDD structure can be suppressed by optimizing the n-dose. Thereby, it is important that the lateral electric field peak remains under the gate.

Low‐frequency 1/f noise in MOSFET’s at low current levels

Low‐frequency 1/f noise in Si n‐channel MOSFET’s is measured at 300 and 77 K. It is found that the equivalent input‐noise resistance Rng increases at low current levels from 100 to 10−2 μA in both the saturation and linear regions. A theory is developed to account for this characteristic, assuming the activated conduction at low electron concentrations due to the surface potential roughness as proposed by Chen and Muller. Theoretical calculations are made for the linear region of operation. Excellent agreement is obtained between the theory and the experiment at both temperatures.

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p+regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n+source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.

VLSI reliability challenges: from device physics to wafer scale systems

The philosophical and practical differences between Japanese and US IC industries in regard to VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing, are discussed. It is suggested that a new approach to VLSI reliability is needed in response to the paradigm shift being brought about by simple scaling limitations, increased process complexity and application of VLSI to advanced systems. An example of this shift is the movement from simple failure analysis by sampling the output of a manufacturing line to the building-in-reliability approach. To introduce and expand on the building-in reliability approach in VLSIs, the authors discuss the required deeper physical understanding of such important processes as hot-carrier effects, dielectrics and metallization. >

Analytical expressions for the static MOS transistor characteristics based on the gradual channel model

Abstract Analytical solutions are derived from Pao and Sahs double integral formula for the theoretical static I–V characteristics of MOS transistors including both the diffusion and drift currents based on the gradual channel model. Expressions for the entire saturation, non-saturation and low level current regions are given, while the specific importance of the theory is seen in the cross-over region between low level and normal operation. Reddi and Sahs formula for channel shrinkage is modified and included to account for the small drain conductance in the saturation region by taking the drain avalanche breakdown voltage into consideration. The solutions are compared with experimental data, and the effectiveness and the limit of the theory is quickly examined.

VLSI reliability challenges: From device physics to wafer scale systems

Abstract The philosophical and practical differences between Japanese and American IC industries concerning VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing are discussed. A new challenging approach to VLSI reliability is now greatly needed in response to the “paradigm shift” now being brought about by simple scaling limitations, increased process complexity, and VLSI application to advanced systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the “building-in-reliability” approach. To pursue this technique, greater importance will be attached to a deeper physical understanding (including frequent use of Computer Aided Design, CAD/ Design Automation, DA) of the significant relationships between the input variables and product reliability, and to total concurrent engineering from research labs to production sites. In addition, distributive quality control management being carried out particularly in Japan, where quality improvement is the common concern for every employeee, may be a key factor in overcoming the more difficult reliability problems in the coming giga-scale ICs. Furthermore, fast new VLSI testing methods and new yield-enhancing redundancy techniques, resulting in cost reduction, will be increasingly needed to achieve high reliability for VLSIs with 109 devices on a single chip.

Design for alpha immunity of MOS dynamic RAM's

Soft error rate(SER) analysis model named HSERAM has been developed to provide a design tool for alpha immunity of MOS dynamic RAMs. The model is verified through the good agreement between the simulated and the measured SER of 64K bit dynamic RAMs. The SER of the metal folded-bit-line structure is compared around 10 times favorably with that of the diffused open-bit-line one in case of the same signal charge. Accelerated testing with increased alpha flux is risky for bit line mode soft error with large signal charge because of few alpha particles of low angle incidence which are most harmful in package mounted devices. Also shown briefly are the effectiveness of a protective coating to reduce SER and the measurement techniques easily equipped to detect 10-5ppm level of U and Th in semiconductor component materials.

Operation model of floating-Si-gate channel-corner-avalanche-transition (FCAT) nonvolatile memory devices

A write/erase model is described for FCAT nonvolatile memory devices which perform write/erase operations with 10–20 V pulses of less than 100-1 μs duration. The amplitude of the threshold voltage shift is analyzed as a function of the source and gate pulse amplitudes using a sample equivalent source circuit. The high level saturated threshold voltage, VTH, obtained by electron injection into the floating gate and the low level saturated threshold voltage, VTL, due to hole injection are shown to be linear functions of VG and VS, and the analysis agrees well with experimental results. The influence of series resistance, including substrate resistance, in the source circuit is also discussed.

Determination of surface state density from gm − VG characteristics of MOSFETs

Abstract The g m - V g characteristics of a MOSFET measured at the room temperature in the transition region between the normal and the low level current regions are compared with the theoretical curve to obtain the surface state density, ρ SS , within a small surface potential interval near the threshold voltage. It is further shown theoretically that the peak value of g m , g m 0 , reduces against the increase of ρ SS by the factor 1/(1 + αρ SS ) where α is a constant, and good agreement is obtained between theory and experiment by using the devices in which surface states are produced by the RF sputter coating with SiO 2 . The gate voltage corresponding to g m0 or g m0 10 is shown to be linearly dependent on ρ SS , but the gate voltage shift is considerably small at the lower current level, indicating the surface state density increasing sharply towards the valence band edge.

Considerations on oxide reliability QC

Engineers involved with oxide reliability have different languages, (1) the breakdown voltage (Vbd) distribution or the defect density at wafer level, (2) the bum-in failure rate analyzed by assuming Weibull distribution, and the field failure rate. To relate these parameters theoretically, the effective oxide thickness, tox-eff, distribution and the basic acceleration models, the E model and the l/E model, were adopted. A simulator is presented that derives the Vbd distribution and the field failure rate from the Weibull distribution of the burn-in failures. For the better use of the theory, we need to accumulate accurate values of acceleration parameters.