Kuniyuki Tani

A pipelined ADC macro design for multiple applications

We present a new design methodology for high-speed Analog-to-Digital Converter (ADC) macros based on our original pipelined 10-bit ADC. With library re-use methodology and performance driven optimization techniques, we have been able to both shorten the design period and to meet application specifications for items such as speed and power consumption. Using this method, we have developed ADC macros from 10-bit to 8-bit and 6-bit. They can be embedded into system LSIs for communication and multimedia applications.

A 10b 50–msample/s CMOS ADC in ASIC process

We have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. With these techniques, we developed a 50 Msample/s 10b CMOS ADC with a 3.3V power supply, In 0.35µm 1-poly 2-Metal ASIC process without a special analog process. This CMOS ADC measures 4.84mm2. The first test chip was fabricated to verify the new architecture and was measured. It shows good linearity of less than ±1LSB and 130mW power consumption at 50MHz sampling.

CD-ROM drive system

We have developed a front-end processor core that can be easily embedded into CD-ROM/DVD drive LSIs. Our new slice level feedback system and performance-driven optimization techniques enabled design of a 3.13 mm/sup 2/, 64X-speed processor for CD-ROM drive. A test chip was implemented in 0.35 /spl mu/m CMOS. Experimental results show that performance exceeds the requirements for 48X and potentially for up to a 64X speed CD-ROM drive system.

A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process

We have developed a 20 Msample/s 10 b CMOS ADC with a 2.4 V power supply, in 0.35 /spl mu/m 1-poly 2-Metal ASIC process without a special analog process, which is suitable for embedding in ASICs because of the small area (4.84 mm/sup 2/) and small power consumption. To realize this ADC we have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. The prototype chip was fabricated and was measured. It shows good linearity of less than /spl plusmn/1 LSB and 28 mW power consumption with 2.4 V at 20 MHz sampling.