Tetsuro Sawai

High-performance GaAs switch IC's fabricated using MESFET's with two kinds of pinch-off voltages and a symmetrical pattern configuration

GaAs MESFET switch ICs operating at low control voltages of 0/-3 V and +3/0 V have been developed for use in Personal Handy Phones using the 1.9 GHz band. The switch ICs have excellent RF characteristics, and have no need for external circuit installation. The unique points of these ICs are the use of GaAs MESFETs with two kinds of pinch-off voltages and a symmetrical source and drain pattern configuration with respect to the gate. The 0/-3 V IC had low insertion loss of 0.55 dB and 0.65 dB, and high isolation of 31 dB and 24 dB at receiving and transmitting operations, respectively. The +3/0 V IC also had excellent characteristics such as insertion loss of 0.73 dB and 0.95 dB, and isolation of 27 dB and 23 dB, respectively. Both ICs had an output power at 1 dB gain compression point of 25.4 dBm and 3rd order intercept point of more than 46 dBm. >

High-performance GaAs switch ICs fabricated using MESFETs with two kinds of pinch-off voltages [for handy phone]

GaAs MESFET switch ICs operating at low control voltages of 0V/-3V and +3V/0V have been developed for use in the personal handy phone using 1.9 GHz band. The switch ICs have excellent RF characteristics, and have no need for external circuit installation. The unique points of these ICs are the use of GaAs MESFETs with two kinds of pinch-off voltages and a symmetrical source and drain pattern configuration with respect to the gate. The 0V/-3V IC had a low insertion loss of 0.55 dB and 0.65 dB, and high isolation of 31 dB and 24 dB at receiving and transmitting operation, respectively. The +3V/0V IC also had excellent characteristics such as insertion loss of 0.73 dB and 0.95 dB, and isolation of 27 dB and 23 dB, respectively. Both ICs had an output power at 1 dB gain compression point of 25.4 dBm and third-order intercept point of more than 46 dBm.<<ETX>>

A high power-added efficiency GaAs power MESFET operating at a very low drain bias for use in L-band medium-power amplifiers

A power MESFET offering a high eta /sub add/ operating at a very low V/sub DD/ has been developed. The MESFET has a buried p-layer and an improved LDD (lightly doped drain) n+ self-aligned structure which include highly electrically activated ion-implanted regions due to rapid thermal-cap annealing using double-layered SiN films deposited by ECR plasma chemical vapor deposition. The device geometries and implantation conditions were optimized to achieve a high V/sub (BR)GDO/ of more than 10 V and a low V/sub K/ of less than 0.5 V, and to minimize the bias dependence of S-parameters. This produced excellent electrical characteristics such as P/sub 0(1dB/)=177 mW (173 mW), eta /sub add/=38.8% (32.6%) at V/sub DD/=3 V (2 V), and I/sub DS/=0.16 A ( approximately 0.4I/sub DSS/) (0.24 A ( approximately 0.6I/sub DSS/)) at 1.9 GHz.<<ETX>>

Integrated passive design library for multilayer PCB

An integrated passives library for a 4-metal layer microstrip PCB-technology has been developed featuring scaleable models for microstrip transmission lines, striplines, discontinuities, integrated single and multi-layer inductors and integrated capacitors. Capacitor Q-factors around 50 are obtained with Q-factors being primarily dominated by the dielectrics loss tangent. Inductor Q-factors around 40 are obtained for single and multi-layer integrated inductors. Bandpass filters, lowpass filters, quadrature couplers and baluns have been designed for the 2.4GHz and 5.2GHz band with good performance. The influence of temperature on the RF performance of integrated inductors, capacitors and an integrated bandpass filter has been evaluated over the 5degC-115degC temperature range

A high efficiency GaAs power amplifier module with a single voltage for digital cellular phone systems

This work describes a two-stage 0.2 cc power amplifier (PA) module with single voltage operation for digital cellular phone system terminals. A new GaAs FET structure enables this operation. To increase power-added efficiency, it is found to be advantageous to use heat spreading with a Cu plate in the cavity and second-order harmonic suppression with the trap capacitor built into the drain bias circuit. Output power of 30.5 dBm with power added efficiency of 54% has been obtained at 1.45 GHz and 3.5 V.

Ultra-compact 1 W GaAs SPDT switch IC

An ultra-compact 1 W GaAs SPDT switch IC operating at +3/0 V is demonstrated. The switch IC consists of multi-gate FETs in which multiple gate electrodes are arranged between source and drain electrodes. By optimizing device parameters, the chip size has been reduced to 1.1 mm/spl times/0.55 mm. Also, the N/sup +/ regions in the FET are connected by fine high-resistance elements to provide a uniform electric potential between gate electrodes. As a result, the linearity of the output power is improved 1 dB at a frequency of 0.9 GHz.

A pipelined ADC macro design for multiple applications

We present a new design methodology for high-speed Analog-to-Digital Converter (ADC) macros based on our original pipelined 10-bit ADC. With library re-use methodology and performance driven optimization techniques, we have been able to both shorten the design period and to meet application specifications for items such as speed and power consumption. Using this method, we have developed ADC macros from 10-bit to 8-bit and 6-bit. They can be embedded into system LSIs for communication and multimedia applications.

A high-performance and miniaturized dual-use (antenna/local) GaAs SPDT switch IC operating at +3 V/0 V

We have developed an ultra-compact dual-use (antenna/local) switch IC for PHS operating at +3/0 V. This IC has a circuit configuration which utilizes MESFETs with two kinds of pinch-off voltages. Additional applied techniques include a circuit design method that employed electromagnetic field analysis, a pull-up method which utilizes forward current flowing in order through the gates of MESFETs, and high isolation characteristic obtained by use of a chip inductor. The insertion loss and isolation characteristics of this IC are, respectively, 0.54 dB and 28.4 dB at 1.9 GHz and 0.48 dB and 30.0 dB at 1.65 GHz. Furthermore, we were able to suppress adjacent channel leakage power to 61.5 dBc at 600-kHz offset during input power of 22 dBm QPSK modulated signals.

A novel design concept for a super compact power amplifier module (SCPAM) using a multilayer substrate

This paper presents a novel circuit and layout design concept for a Super Compact Power Amplifier Module (SCPAM) using a multilayer substrate. This concept enables miniaturization of the module, while continuing to allow easy design and good performance. A 0.04 cc 1 W class module for mobile communication systems is demonstrated. A 0.02 cc module including this concept is also proposed.

CD-ROM drive system

We have developed a front-end processor core that can be easily embedded into CD-ROM/DVD drive LSIs. Our new slice level feedback system and performance-driven optimization techniques enabled design of a 3.13 mm/sup 2/, 64X-speed processor for CD-ROM drive. A test chip was implemented in 0.35 /spl mu/m CMOS. Experimental results show that performance exceeds the requirements for 48X and potentially for up to a 64X speed CD-ROM drive system.