Ayman Shafik

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

Photonic interconnects are a promising technology to meet the bandwidth demands of next-generation high-performance computing systems. This paper presents silicon photonic transceiver circuits for a microring resonator-based optical interconnect architecture in a 1 V standard 65 nm CMOS technology. The transmitter circuits incorporate high-swing ( 2Vpp and 4Vpp) drivers with nonlinear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 Gb/s operation, the 4Vpp transmitter achieves 12.7 dB extinction ratio with 4.04 mW power consumption, excluding laser power, when driving wire-bonded modulators designed in a 130 nm SOI process, while a 0.28 nm tuning range is obtained at 6.8 μW/GHz efficiency with the bias-based tuning scheme implemented with the 2Vpp transmitter. When tested with a wire-bonded 150 fF p-i-n photodetector, the receiver achieves -9 dBm sensitivity at a BER=10-9 and consumes 2.2 mW at 8 Gb/s. Testing with an on-die test structure emulating a low-capacitance waveguide photodetector yields 17 μApp sensitivity at 10 Gb/s and more than 40% power reduction with higher input current levels.

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver

Silicon photonic links based on ring-resonator devices provide a unique opportunity to deliver distance-independent connectivity, whose pin-bandwidth scales with the degree of wavelength-division multiplexing. However, reliability and robustness are major challenges to widespread adoption of ring-based silicon photonics. In this work, a CMOS photonic transceiver architecture is demonstrated that incorporates the following enhancements: transmitters with independent dual-edge pre-emphasis to compensate for modulator bandwidth limitations; a bias-based tuning loop to calibrate for resonance wavelength variations; and an adaptive sensitivity-bandwidth receiver that can self-adapt for insitu variations in input capacitance, modulator/photodetector performance, and link budget.

A WDM silicon photonic transmitter based on carrier-injection microring modulators

We present a 5 × 10 Gbps WDM silicon photonic transmitter based on carrier-injection type microring modulators. Resonant wavelengths can be adjusted by both thermal heaters and bias tuning.

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS

Silicon photonics devices offer promising solution to meet the growing bandwidth demands of next-generation interconnects. This paper presents a 5 × 25 Gb/s carrier-depletion microring-based wavelength-division multiplexing (WDM) transmitter in 65 nm CMOS. An AC-coupled differential driver is proposed to realize 4 × VDD output swing as well as tunable DC-biasing. The proposed transmitter incorporates 2-tap asymmetric pre-emphasis to effectively cancel the optical nonlinearity of the ring modulator. An average-power-based dynamic wavelength stabilization loop is also demonstrated to compensate for thermal induced resonant wavelength drift. At 25 Gb/s operation, each transmitter channel consumes 113.5 mW and maintains 7 dB extinction ratio with a 4.4 V pp-diff output swing in the presence of thermal fluctuations.

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization

Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1-3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity.

A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications

High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approximation-based ADC front-end that efficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1.1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm2 core ADC area. The effectiveness of the embedded FFE and DFE is demonstrated with significant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.

A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10-9. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm 2 area.

Embedded equalization for ADC-based serial I/O receivers

In this paper, the performance impact of embedding partial equalization in ADC-based receivers is analyzed. A hybrid ADC receiver architecture which includes embedded equalization and selective digital equalization power-down based on threshold detection is proposed.

25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization

A 25Gb/s hybrid-integrated microring receiver which includes a thermal tuning loop that stabilizes the drop filter resonance wavelength is implemented. The multi-channel 65nm CMOS source-synchronous receiver achieves -8.2 dBm sensitivity at BER <;10-12 and 0.68pJ/b.

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS

Silicon photonic microring modulators (MRMs) offer a promising approach for realizing energy-efficient wavelength-division multiplexing (WDM) optical interconnects. For data-rates greater than 10Gb/s, depletion-mode MRMs are generally preferred over their injection-mode counterparts due to their shorter carrier lifetimes and resulting higher bandwidths. Unfortunately, these depletion-mode MRMs typically exhibit low PN junction tunability, thereby requiring higher modulation voltages in order to provide >6dB extinction ratios (ER). Furthermore, negative DC-biasing of the MRMs is necessary to maintain reverse-biased depletion-mode operation. In this work, a 5×25Gb/s hybrid-integrated MRM WDM transmitter is demonstrated that incorporates the following key advances: 1) an AC-coupled differential output driver that applies a 4.4Vpp-diff output-swing on the MRM while providing a tunable on-chip negative DC-bias; 2) a 2-tap non-linear digital FFE that compensates for optical-dynamics-induced bandwidth limitations; 3) a dynamic thermal tuning loop that stabilizes the MRM by minimizing thermally-induced wavelength fluctuations.