Kuo-Tung Chang

Process integration for Robust Contact 1 module of high density Floating Gate Memory device

In this presentation, we describe the process integration of a robust Contact One module in a high density floating gate device. Comprehensive process window studies using critical dimension as the control parameter identified the main process limiters and defined the countermeasures for process optimizations. With this Contact One Module as one of the critical operations, good wafer electrical test results and high sort yield have been achieved.

Highly scalable and manufacturable heterogeneous charge trap NAND technology

For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product performance, reliability, and manufacturability demonstrated at the 43nm node, in conjunction with the planar cell architecture have laid the foundation for scaling to <; 20nm.

Eliminating Word Line Bending In Floating Gate NOR Flash Memory To Reduce Array Size and Improve Manufacturability

In floating gate (FG) NOR flash memory arrays, word lines (WL) bend at Vss columns to accommodate the Vss contacts. As the memory cell is scaled down, patterning of the WL bending becomes more and more challenging. Furthermore, to ensure that the WL bending does not extend to the adjacent memory cells to cause abnormal electrical characteristics of the adjacent cells, we have to increase the Vss column width to three or more pitches. The wider Vss columns result in unequal line and spacing, which makes a significant impact on the process window of several modules. Therefore, the WL bending is a process limiter to core cell scaling and manufacturing. In this work, we have succeeded in a device approach to eliminate the WL bending by an additional mask and implant to connect Vss lines and contacts through conductive Vss transistors. The new memory array without WL bending shows comparable device performance and improves manufacturability significantly.