Timothy Thurgate

Selective erasure of a non-volatile memory cell of a flash memory device

Process for reduction of capacitance of a bitline for a non-volatile memory cell

Method of programming a non-volatile memory cell using a vertical electric field

Nitride plug to reduce gate edge lifting

Very low thermal budget channel implant process for semiconductors

Memory device with an alternating Vss interconnection

Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell

Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing

Diode fabrication for ESD/EOS protection

Two bit flash cell with two floating gate regions